<s id="ugmqc"></s> This file is used to transfer p2s data in a Spartan 3e
標簽： transfer Spartan This file
上傳時間： 2014-01-01
上傳用戶：大三三
Souce Code and sample to transfer SQL Server database to SqlServer Compact edition database. C#, dotNet framework
標簽： database SqlServer transfer Compact
上傳時間： 2013-12-24
上傳用戶：阿四AIR
Browser-based (HTTP) file uploading is a great way to transfer arbitrary files from a client machine to the Web server which adds another dimension to Web-based applications.
標簽： Browser-based arbitrary uploading transfer
上傳時間： 2017-08-21
上傳用戶：13188549192
it bout file transfer this is about client and server
標簽： transfer client server about
上傳時間： 2017-09-20
上傳用戶：xymbian
JPEG2000是由ISO/ITU-T組織下的IEC JTC1/SC29/WG1小組制定的下一代靜止圖像壓縮標準.與JPEG(Joint Photographic Experts Group)相比,JPEG2000能夠提供更好的數據壓縮比,并且提供了一些JPEG所不具有的功能[1].JPEG2000具有的多種特性使得它具有廣泛的應用前景.但是,JPEG2000是一個復雜編碼系統,目前為止的軟件實現方案的執行時間和所需的存儲量較大,若想將JPEG2000應用于實際中,有著較大的困難,而用硬件電路實現JPEG2000或者其中的某些模塊,必然能夠減少JPEG200的執行時間,因而具有重要的意義.本文首先簡單介紹了JPEG2000這一新的靜止圖像壓縮標準,然后對算術編碼的原理及實現算法進行了深入的研究,并重點探討了JPEG2000中算術編碼的硬件實現問題,給出了一種硬件最優化的算術編碼實現方案.最后使用硬件描述語言(Very High Speed Integrated Circuit Hardware Description Language,VHDL)在寄存器傳輸級(Register transfer Level,RTL描述了該硬件最優化的算術編碼實現方案,并以Altera 20K200E FPGA為基礎,在Active-HDL環境中進行了功能仿真,在Quartus Ⅱ集成開發環境下完成了綜合以及后仿真,綜合得到的最高工作時鐘頻率達45.81MHz.在相同的輸入條件下,輸出結果表明,本文設計的硬件算術編碼器與實現JPEG2000的軟件:Jasper[2]中的算術編碼模塊相比,處理時間縮短了30﹪左右.因而本文的研究對于JPEG2000應用于數字監控系統等實際應用有著重要的意義.
上傳時間： 2013-05-16
上傳用戶：671145514
隨著電子技術和EDA技術的發展,大規模可編程邏輯器件PLD(Programmable Logic Device)、現場可編程門陣列FPGA(Field Programmable Gates Array)完全可以取代大規模集成電路芯片,實現計算機可編程接口芯片的功能,并可將若干接口電路的功能集成到一片PLD或FPGA中.基于大規模PLD或FPGA的計算機接口電路不僅具有集成度高、體積小和功耗低等優點,而且還具有獨特的用戶可編程能力,從而實現計算機系統的功能重構.該課題以Altera公司FPGA(FLEX10K)系列產品為載體,在MAX+PLUSⅡ開發環境下采用VHDL語言,設計并實現了計算機可編程并行接芯片8255的功能.設計采用VHDL的結構描述風格,依據芯片功能將系統劃分為內核和外圍邏輯兩大模塊,其中內核模塊又分為RORT A、RORT B、OROT C和Control模塊,每個底層模塊采用RTL(Registers transfer Language)級描述,整體生成采用MAX+PLUSⅡ的圖形輸入法.通過波形仿真、下載芯片的測試,完成了計算機可編程并行接芯片8255的功能.
上傳時間： 2013-06-08
上傳用戶：asddsd
·ITU的G.729A編碼庫(可以將PCM轉化為G.729格式)-ITU G729 annex A lib file ,can transfer PCM file format to G729 format
上傳時間： 2013-06-13
上傳用戶：幾何公差
為了滿足現代高速通信中頻率快速轉換的需求，基于坐標旋轉數字計算（CORDIC，Coordinate Rotation Digital Computer）算法完成正交直接數字頻率合成（ODDFS，Orthogonal Direct Digital Frequency Synthesizer）電路設計方案。采用MATLAB和Xilinx System Generator開發工具搭建電路的系統模型，通過現場可編程門陣列（FPGA，Field Programmable Gate Array）完成電路的寄存器傳輸級（RTL，Register transfer Level）驗證，仿真結果表明電路設計具有很高的有效性和可行性。
上傳時間： 2013-11-09
上傳用戶：hfnishi
Linear Technology’s High Frequency Product lineupincludes a variety of RF I/Q modulators. The purpose ofthis application note is to illustrate the circuits requiredto interface these modulators with several popular D/Aconverters. Such circuits typically are required to maximizethe voltage transfer from the DAC to the baseband inputsof the modulator, as well as provide some reconstructionfi ltering.
上傳時間： 2013-10-19
上傳用戶：FreeSky
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
標簽： Converters Defini DAC
上傳時間： 2013-10-30
上傳用戶：stvnash
