本設(shè)計(jì)基于MSP430F161x/261x + CC2420/2520實(shí)驗(yàn)板，給出了物聯(lián)網(wǎng)感知層的一些基本操作，包括傳感器數(shù)據(jù)獲取和低功耗無線數(shù)據(jù)通信兩個(gè)方面。特別是對(duì)MSP430和CC2420/2520的配合給出了較為詳細(xì)的說明及例程。由華東師范大學(xué)TI MSP430聯(lián)合實(shí)驗(yàn)室提供。
上傳時(shí)間： 2013-11-06
上傳用戶：qw12
模擬串口就是利用51的兩個(gè)輸入輸出引腳如P1.0和P1.1,置1或0分別代表高低電平,也就是串口通信中所說的位,如起始位用低電平,則將其置0,停止位為高電平,則將其置1,各種數(shù)據(jù)位和校驗(yàn)位則根據(jù)情況置1或置0。至于串口通信的波特率,說到底只是每位電平持續(xù)的時(shí)間,波特率越高,持續(xù)的時(shí)間越短。如波特率為9600BPS,即每一位傳送時(shí)間為1000ms/9600=0.104ms,即位與位之間的延時(shí)為為0.104毫秒。單片機(jī)的延時(shí)是通過執(zhí)行若干條指令來達(dá)到目的的,因?yàn)槊織l指令為1-3個(gè)指令周期,可即是通過若干個(gè)指令周期來進(jìn)行延時(shí)的,單片機(jī)常用11.0592M的的晶振,現(xiàn)在我要告訴你這個(gè)奇怪?jǐn)?shù)字的來歷。用此頻率則每個(gè)指令周期的時(shí)間為(12/11.0592)us,那么波特率為9600BPS每位要間融多少個(gè)指令周期呢？
上傳時(shí)間： 2013-10-29
上傳用戶：zw380105939
特點(diǎn)： • 8/10 位精度 • 7 us, 10-位單次轉(zhuǎn)換時(shí)間. • 采樣緩沖放大器 • 可編程采樣時(shí)間 • 左/右 對(duì)齊, 有符號(hào)/無符號(hào)結(jié)果數(shù)據(jù) • 外部觸發(fā)控制 • 轉(zhuǎn)換完成中斷 • 模擬輸入8通道復(fù)用 • 模擬/數(shù)字輸入引腳復(fù)用 • 1到8轉(zhuǎn)換序列長度 • 連續(xù)轉(zhuǎn)換模式 • 多通道掃描方式
上傳時(shí)間： 2014-12-28
上傳用戶：88mao
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽： C16x 微控制器 輸入信號(hào) 時(shí)序圖
上傳時(shí)間： 2014-04-02
上傳用戶：han_zh
#include <reg51.h>#include<intrins.h> #define BusY1 (DQ1==0) sbit DQ1 = P0^4; unsigned char idata TMP; unsigned char idata TMP_d; unsigned char f; void wr_ds18_1(char dat);unsigned char rd_ds18_1(); /***************延時(shí)程序，單位us,大于10us*************/void time_delay(unsigned char time){ time=time-10; time=time/6; while(time!=0)time--;} /*****************************************************//* reset ds18b20 *//*****************************************************/void ds_reset_1(void){ unsigned char idata count=0; DQ1=0; time_delay(240); time_delay(240); DQ1=1; return;}
上傳時(shí)間： 2013-10-29
上傳用戶：sssnaxie
基于usB接口的數(shù)據(jù)采集模塊的設(shè)計(jì)與實(shí)現(xiàn)Design and Implementation of usB-Based Data Acquisition Module路 永 伸(天津科技大學(xué)電子信息與自動(dòng)化學(xué)院，天津300222)摘要文中給出基于usB接口的數(shù)據(jù)采集模塊的設(shè)計(jì)與實(shí)現(xiàn)。硬件設(shè)計(jì)采用以Adpc831與PDIusBDI2為主的器件進(jìn)行硬件設(shè)計(jì)，采用Windriver開發(fā)usB驅(qū)動(dòng)，并用Visual C十十6.0對(duì)主機(jī)軟件中硬件接口操作部分進(jìn)行動(dòng)態(tài)鏈接庫封裝。關(guān)鍵詞usB 數(shù)據(jù)采集Adpc831 PDNSBDI2 Windriver動(dòng)態(tài)鏈接庫Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTusBD12i sused for hardware design. The usB drive is developed場Wmdriver, and the operation on the hardware interface is packaged into Dynamic Link Libraries場Visual C++6.0. Keywords usB DataA cquisition Adttc831 PDfusBD12 Windriver0 引言us B總 線 是新一代接口總線，最初推出的目的是為了統(tǒng)一取代PC機(jī)的各類外設(shè)接口，迄今經(jīng)歷了1.0,1.1與2.0版本3個(gè)標(biāo)準(zhǔn)。在國內(nèi)基于usB總線的相關(guān)設(shè)計(jì)與開發(fā)也得到了快速的發(fā)展，很多設(shè)計(jì)者從各自的應(yīng)用領(lǐng)域，用不同方案設(shè)計(jì)出了相應(yīng)的裝置[1,2]。數(shù)據(jù)采集是工業(yè)控制中一個(gè)普遍而重要的環(huán)節(jié)，因此開發(fā)基于usB接口的數(shù)據(jù)采集模塊具有很強(qiáng)的現(xiàn)實(shí)應(yīng)用意義。雖然 us B總線標(biāo)準(zhǔn)已經(jīng)發(fā)展到2.0版本，但由于工業(yè)控制現(xiàn)場干擾信號(hào)的情況比較復(fù)雜，高速數(shù)據(jù)傳輸?shù)目煽啃圆蝗菀妆槐ＷC，并且很多場合對(duì)數(shù)據(jù)采集的實(shí)時(shí)性要求并不高，開發(fā)2.0標(biāo)準(zhǔn)產(chǎn)品的成本又較1.1標(biāo)準(zhǔn)產(chǎn)品高，所以筆者認(rèn)為，在工業(yè)控制領(lǐng)域，目前開發(fā)基于usB總線1.1標(biāo)準(zhǔn)實(shí)現(xiàn)的數(shù)據(jù)采集模塊的實(shí)用意義大于相應(yīng)2.0標(biāo)準(zhǔn)模塊。
標(biāo)簽： usB 接口 數(shù)據(jù)采集模塊
上傳時(shí)間： 2013-10-23
上傳用戶：q3290766
摘 要 瞬態(tài)仿真領(lǐng)域的許多工作需要獲得可視化數(shù)據(jù), 仿真電路不能將輸出參數(shù)繪制成圖形時(shí)研究工作將受到很大影響. 而權(quán)威電路仿真軟件PSpice 在這個(gè)方面不盡如人意. 本文提出了一種有效的解決辦法: 通過MATLAB 編程搭建一個(gè)PSpice 與MATLAB 的數(shù)據(jù)接口,使PSpice輸出數(shù)據(jù)文件可以導(dǎo)入到MATLAB中繪制圖形. 這令我們能夠很方便地獲得數(shù)據(jù)的規(guī)律以有效地分析仿真結(jié)果, 這項(xiàng)技術(shù)對(duì)于教學(xué)和工程實(shí)踐都有比較實(shí)際的幫助.關(guān)鍵詞: 瞬態(tài)仿真 仿真程序 PSpice MATLAB 可視化數(shù)據(jù)The Data Transfer from Pspice to MATLABWu hao Ning yuanzhong Liang yingAbstract Many works in the area of transient simulation has shown how a emulator such asPSpice can be interfaced to an control analysis package such as MATLAB to get viewdata. Thepaper describes how such interfaces can be made using the MATLAB programming. The platformas a typical platform will solve the problem that PSpice software sometimes can not draw the datato a picture. It can make us find the rule from numerous data very expediently, so we can analyzethe outcome of the simulation. And it also can be used in the field of education.Keywords Transient Simulation Emulator PSpice MATLAB Viewdata1 引言科學(xué)研究和工程應(yīng)用常需要進(jìn)行電路仿真 PSpice可進(jìn)行直流 交流 瞬態(tài)等基本電路特性分析 也可進(jìn)行蒙托卡諾 MC 統(tǒng)計(jì)分析 最壞情況 Wcase 分析 優(yōu)化設(shè)計(jì)等復(fù)雜電路特性分析 它是國際上仿真電路的權(quán)威軟件 而MATLAB的主要特點(diǎn)有 高效方便的矩陣和數(shù)組運(yùn)算 編程效率高 結(jié)構(gòu)化面向?qū)ο?方便的繪圖功能 用戶使用方便 工具箱功能強(qiáng)大 兩者各有著重點(diǎn) 兩種軟件結(jié)合應(yīng)用 對(duì)研究工作有很重要的意義香港理工大學(xué)Y. S. LEE 等人首先將PSpice和MATLAB結(jié)合 開發(fā)了電力電子電路優(yōu)化用的CAD 程序MATSPICE[6] 將兩者相結(jié)合的關(guān)鍵在于 如何用MATLAB 獲取PSpice的仿真數(shù)據(jù) 對(duì)此參考文獻(xiàn) 6 里沒有詳細(xì)敘述 本文著重說明用MATLAB 讀取PSpice仿真數(shù)據(jù)的具體方法本論文利用MATLAB對(duì)PSpice仿真出的數(shù)據(jù)處理繪制出后者無法得到或是效果不好的仿真圖形 下面就兩者結(jié)合使用的例子 進(jìn)行具體說明
標(biāo)簽： MATLAB PSpice 數(shù)據(jù) 接口技術(shù)
上傳時(shí)間： 2013-10-20
上傳用戶：wuchunzhong
usB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, usA.
上傳時(shí)間： 2013-10-12
上傳用戶：windgate
In today’s world of modular networking and telecommunications design, it is becomingincreasingly difficult to keep alignment with the many different and often changing interfaces,both inter-board and intra-board. Each manufacturer has their own spin on the way in whichdevices are connected. To satisfy the needs of our customers, we must be able to support alltheir interface requirements. For us to be able to make products for many customers, we mustadopt a modular approach to the design. This modularity is the one issue that drives the majorproblem of shifting our bits from one modular interface to another.
標(biāo)簽： 150 WP 兆兆 網(wǎng)絡(luò)
上傳時(shí)間： 2013-11-25
上傳用戶：suicone
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