基于PIC單片機的脈沖電源:設計了一種金屬凝固過程用脈沖電源。該電源采用PIC16F877作為主控芯片，實現(xiàn)對窄脈沖電流幅值的檢測，以及時電流脈沖幅值根據(jù)模糊PID算法進行閑環(huán)控制。使用結果表明：該電源的輸出脈沖波形良好，電流幅值穩(wěn)定，滿足合金材料凝固過程的工藝要求且運行穩(wěn)定可靠。關鍵詞：脈沖電源；PIC16F877單片機；模糊PID；閑環(huán)控制
Abstract：A kind of pulse power supply was designed which uses in the metal solidification process ．．I11is power supply used PIC16F877 to take the master control chip reali on to the narrow pulse electric current peak-to-peak value examination，carried on the closed-loop control to the electric current pulse peak-to-peak value basis fuzzy PID algorithm．The use result indicated ，this power supply output se profile is good，and the electric current peak-to-p~k value is stable，It satisfies the alloy material solidification process the technological requirement and movement stable reliable，Key words：p se po wer supply；PIC16F877single-chip microcontroller；f r PID；closed-loop control
本文依據(jù)集成電路設計方法學，探討了一種基于標準Intel 8086 微處理器的單芯片計算機平臺的架構。研究了其與SDRAM，8255 并行接口等外圍IP 的集成，并在對AMBA協(xié)議和8086 CPU分析的基礎上，采用遵從AMBA傳輸協(xié)議的系統(tǒng)總線代替?zhèn)鹘y(tǒng)的8086 CPU三總線結構，搭建了基于8086 IP 軟核的單芯片計算機系統(tǒng)，并實現(xiàn)了FPGA 功能演示。關鍵詞：微處理器； SoC；單芯片計算機；AMBA 協(xié)議
Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification
The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
設計一種應用于某全地形ATV車載武器裝置中的中控系統(tǒng)，該系統(tǒng)設計是以TMS320F2812型DSP為核心，采用模塊化設計思想，對其硬件部分進行系統(tǒng)設計，能夠完成對武器裝置高低、回轉方向的運動控制，實現(xiàn)靜止或行進狀態(tài)中對目標物的測距，自動瞄準以及按既定發(fā)射模式發(fā)射彈丸和各項安全性能檢測等功能。通過編制相應的軟件，對其進行系統(tǒng)調試，驗證了該設計運行穩(wěn)定。
Abstract:
A central control system applied to an ATV vehicle weapons is designed. The system design is based on TMS320F2812 DSP as the core， uses modular design for its hardware parts. The central control system can complete the motion control of the level of weapons and equipment， rotation direction， to achieve a state of static or moving objects on the target ranging， auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
為提升虛擬儀器傳輸速率與實時性能，擴展監(jiān)測范圍，在VC的軟件平臺上設計了一種全功能虛擬示波器。與傳統(tǒng)虛擬示波器相比，該系統(tǒng)采用嵌入式系統(tǒng)完成信號采集，采用工業(yè)以太網(wǎng)為傳輸介質，通過線性插值算法和多線程編程思想，實現(xiàn)波形顯示、參數(shù)計算、頻譜分析以及波形存儲及回放功能。實驗結果表明，該虛擬示波器可以實現(xiàn)20 kHz采樣頻率下的波形精確顯示，達到預期的各項指標。
Abstract:
o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
Abstract: The number of uses for microelectromechanical systems (MEMS) is growing—they allow us todo jobs once considered impossible. This tutorial explains the applications for MEMS and the increasingneed to provide precision control and drivers for these devices. Design and manufacturing considerationsare also discussed.
