UART 4 UART參考設(shè)計，Xilinx提供vHDL代碼 uart_vHDl
This zip file contains the following folders:
\vHDl_source -- Source vHDL files:
uart.vHD - top level file
txmit.vHD - transmit portion of uart
rcvr.vHD - - receive portion of uart
\vHDl_testfixture -- vHDL Testbench files. This files only include the testbench behavior, they
do not instantiate the DUT. This can easily be done in a top-level vHDL
file or a schematic. This folder contains the following files:
txmit_tb.vHD -- Test bench for txmit.vHD.
rcvr_tf.vHD -- Test bench for rcvr.vHD.
標簽：
UART
Xilinx
vHDL
參考設(shè)計
上傳時間：
2013-11-02
上傳用戶：18862121743
