a fat12 source code, it is verified for many platform
a fat12 source code, it is verified for many platform...
verified技術(shù)資料
?? 資源總數(shù)：20
?? 源代碼：1549
?? 電路圖：2
?? verified全部資料 (20個(gè))
Pre-designed and pre-verified hardware and software blocks can be combined on chips for many differ
Pre-designed and pre-verified hardware and software blocks can be combined on chips for many differ...
PCI設(shè)計(jì)指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. Th
PCI設(shè)計(jì)指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. Th...
wireless stepper motor verified by kpserver
wireless stepper motor verified by kpserver...
基于DSP Builder數(shù)字信號(hào)處理器的FPGA設(shè)計(jì)
針對(duì)使用硬件描述語(yǔ)言進(jìn)行設(shè)計(jì)存在的問(wèn)題，提出一種基于FPGA并采用DSP Builder作為設(shè)計(jì)工具的數(shù)字信號(hào)處理器設(shè)計(jì)方法。并按照Matlab/Simulink/DSP Builder/Quartu...
BlueCore supports a mechanism called Device Firmware Upgrade (DFU) to enable its software and config
BlueCore supports a mechanism called Device Firmware Upgrade (DFU) to enable its software and config...
THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EX
THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EX...
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM mode...
This chapter contains sample programs for determining capacity. The reader is advised to go through
This chapter contains sample programs for determining capacity. The reader is advised to go through ...
This is GPS Matlab findPreambles finds the first preamble occurrence in the bit stream of each ch
This is GPS Matlab findPreambles finds the first preamble occurrence in the bit stream of each ch...