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標(biāo)簽： bu haoyisi shao ying
上傳時間： 2013-12-26
上傳用戶：極客
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上傳時間： 2014-01-03
上傳用戶：zhyiroy
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上傳時間： 2017-02-20
上傳用戶：bibirnovis
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標(biāo)簽： yejing yong 1602 xian
上傳時間： 2017-06-12
上傳用戶：gaome
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上傳時間： 2017-07-07
上傳用戶：13681659100
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上傳時間： 2013-11-28
上傳用戶：fanboynet
匯編器在微處理器的驗證和應(yīng)用中舉足輕重，如何設(shè)計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統(tǒng)設(shè)計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關(guān)系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發(fā)了一套匯編器系統(tǒng)，具有較高層次上的通用性和可移植性。【關(guān)鍵詞】指令集，CMDL，匯編器，開放式 Design of Retargetable Assembler System Liu Ling Feng wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關(guān)鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
上傳時間： 2013-10-10
上傳用戶：meiguiweishi
FIFO電路(first in，first out)，內(nèi)部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次讀出已經(jīng)寫入的數(shù)據(jù)。因為不存在Address輸入，所以請自行設(shè)計內(nèi)藏的讀寫指針。由FIFO電路輸出的EF信號(表示RAM內(nèi)部的數(shù)據(jù)為空)和FF信號(表示RAM內(nèi)部的數(shù)據(jù)為滿)來表示RAM內(nèi)部的狀態(tài)，并且控制FIFO的輸入信號wen(寫使能)和REN(讀使能)。以及為了更好得控制FIFO電路，AEF(表示RAM內(nèi)部的數(shù)據(jù)即將空)信號也同時輸出。
上傳時間： 2016-02-06
上傳用戶：zhoujunzhen
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