NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上傳時間： 2013-11-15
上傳用戶：zouxinwang
單芯片手機(jī)的優(yōu)點(diǎn)與挑戰(zhàn) 從電信公司到OEM 和ODM 廠商到芯片組供貨商，手機(jī)價值鏈的所有業(yè)者都在努力提高功能整合度，它是手機(jī)降低成本和節(jié)省電路板面積給其它功能的重要關(guān)鍵。自從20 年前出現(xiàn)以來，手機(jī)就以循序漸近的方式逐步提高功能整合，在此過程中并沒有任何一種技術(shù)能夠?qū)崿F(xiàn)功能整合的大躍進(jìn)。
標(biāo)簽： 單芯片手機(jī)
上傳時間： 2014-12-27
上傳用戶：lifangyuan12
C51 中的關(guān)鍵字關(guān)鍵字 用途 說明auto 存儲種類說明 用以說明局部變量，缺省值為此break 程序語句 退出最內(nèi)層循環(huán)case 程序語句 Switch 語句中的選擇項(xiàng)char 數(shù)據(jù)類型說明 單字節(jié)整型數(shù)或字符型數(shù)據(jù)const 存儲類型說明 在程序執(zhí)行過程中不可更改的常量值continue 程序語句 轉(zhuǎn)向下一次循環(huán)default 程序語句 Switch 語句中的失敗選擇項(xiàng)do 程序語句 構(gòu)成do..while 循環(huán)結(jié)構(gòu)double 數(shù)據(jù)類型說明 雙精度浮點(diǎn)數(shù)else 程序語句 構(gòu)成if..else 選擇結(jié)構(gòu)enum 數(shù)據(jù)類型說明 枚舉extern 存儲種類說明 在其他程序模塊中說明了的全局變量flost 數(shù)據(jù)類型說明 單精度浮點(diǎn)數(shù)for 程序語句 構(gòu)成for 循環(huán)結(jié)構(gòu)goto 程序語句 構(gòu)成goto 轉(zhuǎn)移結(jié)構(gòu)if 程序語句 構(gòu)成if..else 選擇結(jié)構(gòu)int 數(shù)據(jù)類型說明 基本整型數(shù)long 數(shù)據(jù)類型說明 長整型數(shù)register 存儲種類說明 使用CPU 內(nèi)部寄存的變量return 程序語句 函數(shù)返回short 數(shù)據(jù)類型說明 短整型數(shù)signed 數(shù)據(jù)類型說明 有符號數(shù)，二進(jìn)制數(shù)據(jù)的最高位為符號位sizeof 運(yùn)算符 計(jì)算表達(dá)式或數(shù)據(jù)類型的字節(jié)數(shù)static 存儲種類說明 靜態(tài)變量struct 數(shù)據(jù)類型說明 結(jié)構(gòu)類型數(shù)據(jù)swicth 程序語句 構(gòu)成switch 選擇結(jié)構(gòu)typedef 數(shù)據(jù)類型說明 重新進(jìn)行數(shù)據(jù)類型定義union 數(shù)據(jù)類型說明 聯(lián)合類型數(shù)據(jù)unsigned 數(shù)據(jù)類型說明 無符號數(shù)數(shù)據(jù)void 數(shù)據(jù)類型說明 無類型數(shù)據(jù)volatile 數(shù)據(jù)類型說明 該變量在程序執(zhí)行中可被隱含地改變while 程序語句 構(gòu)成while 和do..while 循環(huán)結(jié)構(gòu)ANSIC 標(biāo)準(zhǔn)關(guān)鍵字關(guān)鍵字 用途 說明bit 位標(biāo)量聲明 聲明一個位標(biāo)量或位類型的函數(shù)sbit 位標(biāo)量聲明 聲明一個可位尋址變量
標(biāo)簽： C51
上傳時間： 2013-10-08
上傳用戶：waves_0801
AT89C2051驅(qū)動步進(jìn)電機(jī)的電路和源碼:AT89C2051驅(qū)動步進(jìn)電機(jī)的電路和源碼 程序:stepper.c stepper.hex/* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */＃i nclude c:\mc5151io.h /* include i/o header file */ ＃i nclude c:\mc5151reg.hregister unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n;unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400/* flag1 mask byte 0x01 run cw() 0x02 run ccw() */main(){ flag1=0; serinit(9600); disable(); /* no need timer interrupt */ cw_n = n; /* initial step number for cw */ flag1 |=0x01; /* initial enable cw() */while(1){ { tick_wait(); /* wait for 10ms elapsed */energize(); /* round-robin execution the following tasks every 10ms */ cw(); ccw(); } }}cw(){ if((flag1&0x01)!=0) { cw_n--; /* decrement cw step number */ if (cw_n !=0) j++; /* if not zero increment index j */ else {flag1&=~0x01; /* disable cw() execution */ ccw_n = n; /* reload step number to ccw counter */ flag1 |=0x02; /* enable cww() execution */ } }
上傳時間： 2013-11-21
上傳用戶：boyaboy
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
標(biāo)簽： 5channel 9516 PCA I2C
上傳時間： 2013-11-21
上傳用戶：q123321
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標(biāo)簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
The PCA9518 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both thedata (SDA) and the clock (SCL) lines, thus enabling virtuallyunlimited buses of 400 pF.
標(biāo)簽： Expandable 5channel 9518 PCA
上傳時間： 2013-10-23
上傳用戶：dumplin9
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標(biāo)簽： 4channel transla level 9519
上傳時間： 2013-11-19
上傳用戶：jisiwole
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽： MULTICHANNEL 5.5 TO RS
上傳時間： 2013-10-19
上傳用戶：ddddddd
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上傳時間： 2013-10-11
上傳用戶：dianxin61
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