SOC驗(yàn)證方法 - 免費(fèi)下載
教程資料資源
文件大小：4387 K
?? 資源詳細(xì)信息
?? 溫馨提示：本資源由用戶 xueyongyong 上傳分享，僅供學(xué)習(xí)交流使用。如有侵權(quán)，請(qǐng)聯(lián)系我們刪除。
資源簡(jiǎn)介
Prakash Rashinkar has over 15 years experience in system design and verification
of embedded systems for communication satellites, launch vehicles and spacecraft
ground systems, high-performance computing, switching, multimedia, and wireless
applications. Prakash graduated with an MSEE from Regional Engineering College,
Warangal, in India. He lead the team that was responsible for delivering the
methodologies for SOC verification at Cadence Design Systems. Prakash is an
active member of the VSIA Functional Verification DWG. He is currently Architect
in the Vertical Markets and Design Environments Group at Cadence.
of embedded systems for communication satellites, launch vehicles and spacecraft
ground systems, high-performance computing, switching, multimedia, and wireless
applications. Prakash graduated with an MSEE from Regional Engineering College,
Warangal, in India. He lead the team that was responsible for delivering the
methodologies for SOC verification at Cadence Design Systems. Prakash is an
active member of the VSIA Functional Verification DWG. He is currently Architect
in the Vertical Markets and Design Environments Group at Cadence.
立即下載此資源
提示：下載后請(qǐng)用壓縮軟件解壓，推薦使用 WinRAR 或 7-Zip
資源說(shuō)明
下載說(shuō)明
- 下載需消耗 2積分
- 24小時(shí)內(nèi)重復(fù)下載不扣分
- 支持?jǐn)帱c(diǎn)續(xù)傳
- 資源永久有效
使用說(shuō)明
- 下載后用解壓軟件解壓
- 推薦 WinRAR 或 7-Zip
- 如有密碼請(qǐng)查看說(shuō)明
- 解壓后即可使用
積分獲取
- 上傳資源獲得積分
- 每日簽到免費(fèi)領(lǐng)取
- 邀請(qǐng)好友注冊(cè)獎(jiǎng)勵(lì)
- 查看詳情 →