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SOC驗(yàn)證方法

  • 資源大小:4387 K
  • 上傳時(shí)間: 2013-11-19
  • 上傳用戶:茗笑弒痛
  • 資源積分:2 下載積分
  • 標(biāo)      簽: SOC 驗(yàn)證方法

資 源 簡(jiǎn) 介

Prakash Rashinkar has over 15 years experience in system design and verification
of embedded systems for communication satellites, launch vehicles and spacecraft
ground systems, high-performance computing, switching, multimedia, and wireless
applications. Prakash graduated with an MSEE from Regional Engineering College,
Warangal, in India. He lead the team that was responsible for delivering the
methodologies for SOC verification at Cadence Design Systems. Prakash is an
active member of the VSIA Functional Verification DWG. He is currently Architect
in the Vertical Markets and Design Environments Group at Cadence.

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