LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY cla IS
    PORT
        (
        a           : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
        b           : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
        c           : OUT   STD_LOGIC;
        s           : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
END cla;

ARCHITECTURE RTL OF cla IS

    SIGNAL p        : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL g        : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL cc       : STD_LOGIC_VECTOR(8 DOWNTO 0);

BEGIN

    p_g_gen : PROCESS(a,b)
    BEGIN
        FOR i IN 0 TO 7 LOOP
            p(i)    <= a(i) OR b(i);
            g(i)    <= a(i) AND b(i);
        END LOOP;
    END PROCESS;



    cc_gen : PROCESS(p,g,cc)
    BEGIN
        cc(0)   <= '0';
        FOR i IN 0 TO 7 LOOP
            cc(i+1) <= g(i) OR (p(i) AND cc(i));
        END LOOP;
    END PROCESS;

    s_gen : PROCESS(a,b,cc)
    BEGIN
        FOR i IN 0 TO 7 LOOP
            s(i)   <= a(i) XOR b(i) XOR cc(i);
        END LOOP;
    END PROCESS;

    c   <= cc(8);

END RTL;