+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 125     ;
; Total combinational functions     ; 121     ;
;     -- Total 4-input functions    ; 55      ;
;     -- Total 3-input functions    ; 23      ;
;     -- Total 2-input functions    ; 31      ;
;     -- Total 1-input functions    ; 11      ;
;     -- Total 0-input functions    ; 1       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 62      ;
; Total logic cells in carry chains ; 11      ;
; I/O pins                          ; 17      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 62      ;
; Total fan-out                     ; 508     ;
; Average fan-out                   ; 3.58    ;
+-----------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; |hdlc                      ; 125 (1)     ; 62           ; 0           ; 17   ; 0            ; 63 (1)       ; 4 (0)             ; 58 (0)           ; 11 (0)          ; |hdlc                  ;
;    |control:control1|      ; 48 (48)     ; 18           ; 0           ; 0    ; 0            ; 30 (30)      ; 2 (2)             ; 16 (16)          ; 0 (0)           ; |hdlc|control:control1 ;
;    |flag1:flag11|          ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 3 (3)            ; 0 (0)           ; |hdlc|flag1:flag11     ;
;    |free:free1|            ; 9 (9)       ; 5            ; 0           ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |hdlc|free:free1       ;
;    |mux3:mux|              ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |hdlc|mux3:mux         ;
;    |shift32:shift|         ; 61 (61)     ; 35           ; 0           ; 0    ; 0            ; 26 (26)      ; 1 (1)             ; 34 (34)          ; 11 (11)         ; |hdlc|shift32:shift    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------+
; State Machine - |hdlc|shift32:shift|state                       ;
+----------+----------+----------+----------+----------+----------+
; Name     ; state.e4 ; state.e3 ; state.e2 ; state.e1 ; state.e0 ;
+----------+----------+----------+----------+----------+----------+
; state.e4 ; 0        ; 0        ; 0        ; 0        ; 0        ;
; state.e3 ; 1        ; 1        ; 0        ; 0        ; 0        ;
; state.e2 ; 1        ; 0        ; 1        ; 0        ; 0        ;
; state.e1 ; 1        ; 0        ; 0        ; 1        ; 0        ;
; state.e0 ; 1        ; 0        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+----------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; control:control1|en1                          ;   ;
; control:control1|en3                          ;   ;
; Number of user-specified and inferred latches ; 2 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 62    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 9     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 49    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |hdlc|shift32:shift|crc_reg[2]   ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |hdlc|control:control1|count2[3] ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |hdlc|shift32:shift|count1[4]    ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |hdlc|control:control1|count3[3] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |hdlc|flag1:flag11|count[2]      ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |hdlc|shift32:shift|count[3]     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |hdlc|shift32:shift|count[5]     ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |hdlc|free:free1|count[0]        ;
; 4:1                ; 6 bits    ; 12 LEs        ; 0 LEs                ; 12 LEs                 ; Yes        ; |hdlc|control:control1|count1[5] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------+


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: shift32:shift ;
+----------------+----------------------------------+--------+
; Parameter Name ; Value                            ; Type   ;
+----------------+----------------------------------+--------+
; d              ; 11100011111000100101010111111001 ; Binary ;
; e0             ; 00001                            ; Binary ;
; e1             ; 00010                            ; Binary ;
; e2             ; 00100                            ; Binary ;
; e3             ; 01000                            ; Binary ;
; e4             ; 10000                            ; Binary ;
+----------------+----------------------------------+--------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/my_design/hdlc/hdlc.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jul 01 22:51:38 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hdlc -c hdlc
Warning: Verilog HDL net warning at hdlc.v(24): created undeclared net "rd"
Info: Found 1 design units, including 1 entities, in source file hdlc.v
    Info: Found entity 1: hdlc