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--D1_dout is free:free1|dout
--operation mode is normal

D1_dout_lut_out = D1_count[3] & (D1_dout & !D1L01) # !D1_count[3] & D1L9;
D1_dout = DFFEAS(D1_dout_lut_out, clk, VCC, , B1_en3, , , , );


--F1_crcout is shift32:shift|crcout
--operation mode is normal

F1_crcout_lut_out = B1_sel1 & F1L66 # !B1_sel1 & (F1L21);
F1_crcout = DFFEAS(F1_crcout_lut_out, clk, VCC, , F1L36, , , , );


--F1_flag is shift32:shift|flag
--operation mode is normal

F1_flag_lut_out = F1_crcout & (!F1_state.e4);
F1_flag = DFFEAS(F1_flag_lut_out, clk, VCC, , B1_en1, , , , );


--E1L1 is mux3:mux|always0~162
--operation mode is normal

E1L1 = ept & D1_dout # !ept & (F1_crcout & !F1_flag);


--C1_dout is flag1:flag11|dout
--operation mode is normal

C1_dout_lut_out = C1_count[2] & (!C1_count[0] # !C1_count[1]) # !C1_count[2] & (C1_count[1] # C1_count[0]);
C1_dout = DFFEAS(C1_dout_lut_out, clk, VCC, , B1_en2, , , , );


--B1_sel2 is control:control1|sel2
--operation mode is normal

B1_sel2_lut_out = !B1L41 & (B1L15 # B1_en2 & !B1L24);
B1_sel2 = DFFEAS(B1_sel2_lut_out, clk, VCC, , , , , , );


--E1L2 is mux3:mux|always0~163
--operation mode is normal

E1L2 = B1_sel2 & E1L1 # !B1_sel2 & (C1_dout);


--F1L86 is shift32:shift|out~9
--operation mode is normal

F1L86 = F1_crcout & (!F1_flag);


--B1_en2 is control:control1|en2
--operation mode is normal

B1_en2_lut_out = B1L41 # B1_en2 & B1L24 & !B1_en3;
B1_en2 = DFFEAS(B1_en2_lut_out, clk, VCC, , , , , , );


--B1_sel1 is control:control1|sel1
--operation mode is normal

B1_sel1_lut_out = B1L41 # B1_sel1 & (!B1L84 # !B1L42);
B1_sel1 = DFFEAS(B1_sel1_lut_out, clk, VCC, , , , , , );


--D1_count[0] is free:free1|count[0]
--operation mode is normal

D1_count[0]_lut_out = B1_en3 & (D1_count[3] & D1_count[0] & !D1L01 # !D1_count[3] & !D1_count[0]);
D1_count[0] = DFFEAS(D1_count[0]_lut_out, clk, VCC, , , , , , );


--D1_count[1] is free:free1|count[1]
--operation mode is normal

D1_count[1]_lut_out = B1_en3 & (D1_count[1] $ (!D1_count[3] & D1_count[0]));
D1_count[1] = DFFEAS(D1_count[1]_lut_out, clk, VCC, , , , , , );


--D1_count[2] is free:free1|count[2]
--operation mode is normal

D1_count[2]_lut_out = D1L5 & B1_en3;
D1_count[2] = DFFEAS(D1_count[2]_lut_out, clk, VCC, , , , , , );


--D1L9 is free:free1|dout~214
--operation mode is normal

D1L9 = D1_count[0] & (D1_count[1] # D1_count[2]) # !D1_count[0] & (!D1_count[2]);


--D1_count[3] is free:free1|count[3]
--operation mode is normal

D1_count[3]_lut_out = B1_en3 & D1L7;
D1_count[3] = DFFEAS(D1_count[3]_lut_out, clk, VCC, , , , , , );


--D1L01 is free:free1|reduce_nor~15
--operation mode is normal

D1L01 = !D1_count[2] & !D1_count[1] & !D1_count[0];


--F1_dout is shift32:shift|dout
--operation mode is normal

F1_dout_lut_out = F1L66;
F1_dout = DFFEAS(F1_dout_lut_out, clk, VCC, , F1L36, , , , );


--F1_count[5] is shift32:shift|count[5]
--operation mode is normal

F1_count[5]_carry_eqn = F1L24;
F1_count[5]_lut_out = F1_count[5] $ (!F1_count[5]_carry_eqn);
F1_count[5] = DFFEAS(F1_count[5]_lut_out, clk, VCC, , F1L04, ~GND, , , F1L93);


--F1_count1[2] is shift32:shift|count1[2]
--operation mode is normal

F1_count1[2]_lut_out = F1_count[5] # F1L31 # reset1;
F1_count1[2] = DFFEAS(F1_count1[2]_lut_out, clk, VCC, , F1L22, , , , );


--F1_count1[0] is shift32:shift|count1[0]
--operation mode is normal

F1_count1[0]_lut_out = F1_count[5] # F1L51 # reset1;
F1_count1[0] = DFFEAS(F1_count1[0]_lut_out, clk, VCC, , F1L22, , , , );


--F1_count1[1] is shift32:shift|count1[1]
--operation mode is normal

F1_count1[1]_lut_out = F1_count[5] # F1L71 # reset1;
F1_count1[1] = DFFEAS(F1_count1[1]_lut_out, clk, VCC, , F1L22, , , , );


--F1_count1[4] is shift32:shift|count1[4]
--operation mode is normal

F1_count1[4]_lut_out = F1_count[5] # F1L91 # reset1;
F1_count1[4] = DFFEAS(F1_count1[4]_lut_out, clk, VCC, , F1L22, , , , );


--F1_count1[3] is shift32:shift|count1[3]
--operation mode is normal

F1_count1[3]_lut_out = F1_count[5] # F1L02 # reset1;
F1_count1[3] = DFFEAS(F1_count1[3]_lut_out, clk, VCC, , F1L22, , , , );


--F1L1 is shift32:shift|Mux~125
--operation mode is normal

F1L1 = F1_count1[4] & (F1_count1[1] # !F1_count1[0] & !F1_count1[3]) # !F1_count1[4] & (F1_count1[0] $ (F1_count1[1] & !F1_count1[3]));


--F1L56 is shift32:shift|dout~75
--operation mode is normal

F1L56 = F1_count[5] & F1_dout # !F1_count[5] & (!F1_count1[2] & !F1L1);


--F1L2 is shift32:shift|Mux~126
--operation mode is normal

F1L2 = F1_count1[0] & (!F1_count1[4] & F1_count1[3]) # !F1_count1[0] & !F1_count1[1] & F1_count1[4];


--F1L66 is shift32:shift|dout~76
--operation mode is normal

F1L66 = F1L56 # F1_count1[2] & !F1_count[5] & !F1L2;


--F1_crc_reg[10] is shift32:shift|crc_reg[10]
--operation mode is normal

F1_crc_reg[10]_lut_out = reset1 # F1_crc_reg[9];
F1_crc_reg[10] = DFFEAS(F1_crc_reg[10]_lut_out, clk, VCC, , F1L16, , , , );


--F1_count[1] is shift32:shift|count[1]
--operation mode is arithmetic

F1_count[1]_carry_eqn = F1L13;
F1_count[1]_lut_out = F1_count[1] $ (!F1_count[1]_carry_eqn);
F1_count[1] = DFFEAS(F1_count[1]_lut_out, clk, VCC, , F1L04, VCC, , , F1L93);

--F1L33 is shift32:shift|count[1]~247
--operation mode is arithmetic

F1L33 = CARRY(!F1_count[1] & (!F1L13));


--F1_crc_reg[9] is shift32:shift|crc_reg[9]
--operation mode is normal

F1_crc_reg[9]_lut_out = reset1 # F1_crc_reg[8];
F1_crc_reg[9] = DFFEAS(F1_crc_reg[9]_lut_out, clk, VCC, , F1L16, , , , );


--F1_count[0] is shift32:shift|count[0]
--operation mode is arithmetic

F1_count[0]_lut_out = !F1_count[0];
F1_count[0] = DFFEAS(F1_count[0]_lut_out, clk, VCC, , F1L04, VCC, , , F1L93);

--F1L13 is shift32:shift|count[0]~251
--operation mode is arithmetic

F1L13 = CARRY(F1_count[0]);


--F1_crc_reg[8] is shift32:shift|crc_reg[8]
--operation mode is normal

F1_crc_reg[8]_lut_out = reset1 # F1_crc_reg[7];
F1_crc_reg[8] = DFFEAS(F1_crc_reg[8]_lut_out, clk, VCC, , F1L16, , , , );


--F1L3 is shift32:shift|Mux~127
--operation mode is normal

F1L3 = F1_count[1] & (F1_count[0]) # !F1_count[1] & (F1_count[0] & F1_crc_reg[9] # !F1_count[0] & (F1_crc_reg[8]));


--F1_crc_reg[11] is shift32:shift|crc_reg[11]
--operation mode is normal

F1_crc_reg[11]_lut_out = reset1 # F1_crc_reg[10];
F1_crc_reg[11] = DFFEAS(F1_crc_reg[11]_lut_out, clk, VCC, , F1L16, , , , );


--F1L4 is shift32:shift|Mux~128
--operation mode is normal

F1L4 = F1_count[1] & (F1L3 & (F1_crc_reg[11]) # !F1L3 & F1_crc_reg[10]) # !F1_count[1] & (F1L3);


--F1_count[3] is shift32:shift|count[3]
--operation mode is arithmetic

F1_count[3]_carry_eqn = F1L53;
F1_count[3]_lut_out = F1_count[3] $ (!F1_count[3]_carry_eqn);
F1_count[3] = DFFEAS(F1_count[3]_lut_out, clk, VCC, , F1L04, VCC, , , F1L93);

--F1L73 is shift32:shift|count[3]~255
--operation mode is arithmetic

F1L73 = CARRY(!F1_count[3] & (!F1L53));


--F1_crc_reg[5] is shift32:shift|crc_reg[5]
--operation mode is normal

F1_crc_reg[5]_lut_out = F1_crc_reg[15] $ F1_crc_reg[4] $ (F1L66);
F1_crc_reg[5] = DFFEAS(F1_crc_reg[5]_lut_out, clk, VCC, , F1L16, VCC, , , reset1);


--F1_crc_reg[6] is shift32:shift|crc_reg[6]
--operation mode is normal

F1_crc_reg[6]_lut_out = F1_crc_reg[5] # reset1;
F1_crc_reg[6] = DFFEAS(F1_crc_reg[6]_lut_out, clk, VCC, , F1L16, , , , );


--F1_crc_reg[4] is shift32:shift|crc_reg[4]
--operation mode is normal

F1_crc_reg[4]_lut_out = reset1 # F1_crc_reg[3];
F1_crc_reg[4] = DFFEAS(F1_crc_reg[4]_lut_out, clk, VCC, , F1L16, , , , );


--F1L5 is shift32:shift|Mux~129
--operation mode is normal

F1L5 = F1_count[0] & (F1_count[1]) # !F1_count[0] & (F1_count[1] & F1_crc_reg[6] # !F1_count[1] & (F1_crc_reg[4]));


--F1_crc_reg[7] is shift32:shift|crc_reg[7]
--operation mode is normal

F1_crc_reg[7]_lut_out = reset1 # F1_crc_reg[6];
F1_crc_reg[7] = DFFEAS(F1_crc_reg[7]_lut_out, clk, VCC, , F1L16, , , , );


--F1L6 is shift32:shift|Mux~130
--operation mode is normal

F1L6 = F1_count[0] & (F1L5 & (F1_crc_reg[7]) # !F1L5 & F1_crc_reg[5]) # !F1_count[0] & (F1L5);


--F1_count[2] is shift32:shift|count[2]
--operation mode is arithmetic

F1_count[2]_carry_eqn = F1L33;
F1_count[2]_lut_out = F1_count[2] $ (F1_count[2]_carry_eqn);
F1_count[2] = DFFEAS(F1_count[2]_lut_out, clk, VCC, , F1L04, VCC, , , F1L93);

--F1L53 is shift32:shift|count[2]~259
--operation mode is arithmetic

F1L53 = CARRY(F1_count[2] # !F1L33);


--F1_crc_reg[2] is shift32:shift|crc_reg[2]
--operation mode is normal

F1_crc_reg[2]_lut_out = reset1 # F1_crc_reg[1];
F1_crc_reg[2] = DFFEAS(F1_crc_reg[2]_lut_out, clk, VCC, , F1L16, , , , );


--F1_crc_reg[1] is shift32:shift|crc_reg[1]
--operation mode is normal

F1_crc_reg[1]_lut_out = F1_crc_reg[0] # reset1;
F1_crc_reg[1] = DFFEAS(F1_crc_reg[1]_lut_out, clk, VCC, , F1L16, , , , );


--F1_crc_reg[0] is shift32:shift|crc_reg[0]
--operation mode is normal

F1_crc_reg[0]_lut_out = F1_crc_reg[15] $ F1L66;
F1_crc_reg[0] = DFFEAS(F1_crc_reg[0]_lut_out, clk, VCC, , F1L16, VCC, , , reset1);


--F1L7 is shift32:shift|Mux~131
--operation mode is normal

F1L7 = F1_count[1] & (F1_count[0]) # !F1_count[1] & (F1_count[0] & F1_crc_reg[1] # !F1_count[0] & (F1_crc_reg[0]));


--F1_crc_reg[3] is shift32:shift|crc_reg[3]
--operation mode is normal

F1_crc_reg[3]_lut_out = reset1 # F1_crc_reg[2];
F1_crc_reg[3] = DFFEAS(F1_crc_reg[3]_lut_out, clk, VCC, , F1L16, , , , );


--F1L8 is shift32:shift|Mux~132
--operation mode is normal

F1L8 = F1_count[1] & (F1L7 & (F1_crc_reg[3]) # !F1L7 & F1_crc_reg[2]) # !F1_count[1] & (F1L7);


--F1L9 is shift32:shift|Mux~133
--operation mode is normal

F1L9 = F1_count[3] & (F1_count[2]) # !F1_count[3] & (F1_count[2] & F1L6 # !F1_count[2] & (F1L8));


--F1_crc_reg[13] is shift32:shift|crc_reg[13]
--operation mode is normal

F1_crc_reg[13]_lut_out = F1_crc_reg[12] # reset1;
F1_crc_reg[13] = DFFEAS(F1_crc_reg[13]_lut_out, clk, VCC, , F1L16, , , , );


--F1_crc_reg[14] is shift32:shift|crc_reg[14]
--operation mode is normal

F1_crc_reg[14]_lut_out = reset1 # F1_crc_reg[13];
F1_crc_reg[14] = DFFEAS(F1_crc_reg[14]_lut_out, clk, VCC, , F1L16, , , , );


--F1_crc_reg[12] is shift32:shift|crc_reg[12]
--operation mode is normal

F1_crc_reg[12]_lut_out = F1_crc_reg[15] $ F1_crc_reg[11] $ (F1L66);
F1_crc_reg[12] = DFFEAS(F1_crc_reg[12]_lut_out, clk, VCC, , F1L16, VCC, , , reset1);


--F1L01 is shift32:shift|Mux~134
--operation mode is normal

F1L01 = F1_count[0] & (F1_count[1]) # !F1_count[0] & (F1_count[1] & F1_crc_reg[14] # !F1_count[1] & (F1_crc_reg[12]));


--F1_crc_reg[15] is shift32:shift|crc_reg[15]
--operation mode is normal

F1_crc_reg[15]_lut_out = reset1 # F1_crc_reg[14];
F1_crc_reg[15] = DFFEAS(F1_crc_reg[15]_lut_out, clk, VCC, , F1L16, , , , );


--F1L11 is shift32:shift|Mux~135
--operation mode is normal

F1L11 = F1_count[0] & (F1L01 & (F1_crc_reg[15]) # !F1L01 & F1_crc_reg[13]) # !F1_count[0] & (F1L01);


--F1L21 is shift32:shift|Mux~136
--operation mode is normal

F1L21 = F1_count[3] & (F1L9 & (F1L11) # !F1L9 & F1L4) # !F1_count[3] & (F1L9);


--F1L36 is shift32:shift|crcout~2
--operation mode is normal

F1L36 = B1_en1 & (!F1_flag & !reset1);


--F1_state.e4 is shift32:shift|state.e4
--operation mode is normal

F1_state.e4_lut_out = !F1_state.e3 # !F1_crcout;
F1_state.e4 = DFFEAS(F1_state.e4_lut_out, clk, VCC, , B1_en1, , , , );


--C1_count[2] is flag1:flag11|count[2]
--operation mode is normal

C1_count[2]_lut_out = C1_count[2] $ (C1_count[1] & C1_count[0]);
C1_count[2] = DFFEAS(C1_count[2]_lut_out, clk, VCC, , B1_en2, , , , );


--C1_count[1] is flag1:flag11|count[1]
--operation mode is normal

C1_count[1]_lut_out = C1_count[1] $ C1_count[0];
C1_count[1] = DFFEAS(C1_count[1]_lut_out, clk, VCC, , B1_en2, , , , );


--C1_count[0] is flag1:flag11|count[0]
--operation mode is normal

C1_count[0]_lut_out = !C1_count[0];
C1_count[0] = DFFEAS(C1_count[0]_lut_out, clk, VCC, , B1_en2, , , , );


--B1L15 is control:control1|sel2~96
--operation mode is normal

B1L15 = B1_sel2 # B1_en3;


--B1_count2[2] is control:control1|count2[2]
--operation mode is normal

B1_count2[2]_lut_out = !B1_reset2 & !reset1 & (B1_count2[2] $ B1L4);
B1_count2[2] = DFFEAS(B1_count2[2]_lut_out, clk, VCC, , B1L13, , , , );


--B1_count2[1] is control:control1|count2[1]
--operation mode is normal

B1_count2[1]_lut_out = !B1L41 & (B1_count2[1] $ (!B1_count2[3] & B1_count2[0]));
B1_count2[1] = DFFEAS(B1_count2[1]_lut_out, clk, VCC, , B1L13, , , , );


--B1_count2[0] is control:control1|count2[0]
--operation mode is normal

B1_count2[0]_lut_out = !B1_reset2 & !reset1 & (B1_count2[3] $ !B1_count2[0]);
B1_count2[0] = DFFEAS(B1_count2[0]_lut_out, clk, VCC, , B1L13, , , , );


--B1_count2[3] is control:control1|count2[3]
--operation mode is normal

B1_count2[3]_lut_out = !B1L41 & (B1_count2[3] $ (B1_count2[2] & B1L4));
B1_count2[3] = DFFEAS(B1_count2[3]_lut_out, clk, VCC, , B1L13, , , , );


--B1L24 is control:control1|reduce_nor~31
--operation mode is normal

B1L24 = B1_count2[2] # B1_count2[1] # B1_count2[0] # !B1_count2[3];