{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 01 22:52:45 2007 " "Info: Processing started: Sun Jul 01 22:52:45 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off hdlc -c hdlc --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hdlc -c hdlc --generate_functional_sim_netlist" {  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "rd hdlc.v(24) " "Warning: Verilog HDL net warning at hdlc.v(24): created undeclared net \"rd\"" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 24 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hdlc.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file hdlc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hdlc " "Info: Found entity 1: hdlc" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 12 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "crc1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file crc1.v" { { "Info" "ISGN_ENTITY_NAME" "1 crc1 " "Info: Found entity 1: crc1" {  } { { "crc1.v" "" { Text "F:/my_design/hdlc/crc1.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "control.v(27) " "Warning: (10268) Verilog HDL information at control.v(27): Always Construct contains both blocking and non-blocking assignments" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 27 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control.v" { { "Info" "ISGN_ENTITY_NAME" "1 control " "Info: Found entity 1: control" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "flag1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file flag1.v" { { "Info" "ISGN_ENTITY_NAME" "1 flag1 " "Info: Found entity 1: flag1" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mux3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mux3.v" { { "Info" "ISGN_ENTITY_NAME" "1 mux3 " "Info: Found entity 1: mux3" {  } { { "mux3.v" "" { Text "F:/my_design/hdlc/mux3.v" 7 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "free.v(14) " "Warning: (10268) Verilog HDL information at free.v(14): Always Construct contains both blocking and non-blocking assignments" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 14 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "free.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file free.v" { { "Info" "ISGN_ENTITY_NAME" "1 free " "Info: Found entity 1: free" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test501.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file test501.v" { { "Info" "ISGN_ENTITY_NAME" "1 test501 " "Info: Found entity 1: test501" {  } { { "test501.v" "" { Text "F:/my_design/hdlc/test501.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tian0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file tian0.v" { { "Info" "ISGN_ENTITY_NAME" "1 tian0 " "Info: Found entity 1: tian0" {  } { { "tian0.v" "" { Text "F:/my_design/hdlc/tian0.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "shift32.v(94) " "Warning: (10268) Verilog HDL information at shift32.v(94): Always Construct contains both blocking and non-blocking assignments" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "shift32.v(146) " "Warning: (10268) Verilog HDL information at shift32.v(146): Always Construct contains both blocking and non-blocking assignments" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 146 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shift32.v" { { "Info" "ISGN_ENTITY_NAME" "1 shift32 " "Info: Found entity 1: shift32" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "hdlc " "Info: Elaborating entity \"hdlc\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "din hdlc.v(14) " "Warning: Output port \"din\" at hdlc.v(14) has no driver" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "sel3 hdlc.v(15) " "Warning: Output port \"sel3\" at hdlc.v(15) has no driver" {  } { { "hdlc.v" "" { Text "F:/my_design/hdlc/hdlc.v" 15 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift32 shift32:shift " "Info: Elaborating entity \"shift32\" for hierarchy \"shift32:shift\"" {  } { { "hdlc.v" "shift" { Text "F:/my_design/hdlc/hdlc.v" 17 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 shift32.v(110) " "Warning: Verilog HDL assignment warning at shift32.v(110): truncated value with size 32 to match size of target (6)" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 shift32.v(112) " "Warning: Verilog HDL assignment warning at shift32.v(112): truncated value with size 32 to match size of target (6)" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 112 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 shift32.v(119) " "Warning: Verilog HDL assignment warning at shift32.v(119): truncated value with size 32 to match size of target (6)" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 119 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 shift32.v(121) " "Warning: Verilog HDL assignment warning at shift32.v(121): truncated value with size 32 to match size of target (6)" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 121 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 shift32.v(140) " "Warning: Verilog HDL assignment warning at shift32.v(140): truncated value with size 32 to match size of target (6)" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 140 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 shift32.v(141) " "Warning: Verilog HDL assignment warning at shift32.v(141): truncated value with size 32 to match size of target (6)" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 141 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "clkout shift32.v(4) " "Warning: Output port \"clkout\" at shift32.v(4) has no driver" {  } { { "shift32.v" "" { Text "F:/my_design/hdlc/shift32.v" 4 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "flag1 flag1:flag11 " "Info: Elaborating entity \"flag1\" for hierarchy \"flag1:flag11\"" {  } { { "hdlc.v" "flag11" { Text "F:/my_design/hdlc/hdlc.v" 18 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 flag1.v(17) " "Warning: Verilog HDL assignment warning at flag1.v(17): truncated value with size 32 to match size of target (4)" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 flag1.v(18) " "Warning: Verilog HDL assignment warning at flag1.v(18): truncated value with size 32 to match size of target (1)" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 flag1.v(21) " "Warning: Verilog HDL assignment warning at flag1.v(21): truncated value with size 32 to match size of target (4)" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 flag1.v(22) " "Warning: Verilog HDL assignment warning at flag1.v(22): truncated value with size 32 to match size of target (1)" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 flag1.v(25) " "Warning: Verilog HDL assignment warning at flag1.v(25): truncated value with size 32 to match size of target (4)" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 flag1.v(26) " "Warning: Verilog HDL assignment warning at flag1.v(26): truncated value with size 32 to match size of target (1)" {  } { { "flag1.v" "" { Text "F:/my_design/hdlc/flag1.v" 26 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "free free:free1 " "Info: Elaborating entity \"free\" for hierarchy \"free:free1\"" {  } { { "hdlc.v" "free1" { Text "F:/my_design/hdlc/hdlc.v" 19 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 free.v(19) " "Warning: Verilog HDL assignment warning at free.v(19): truncated value with size 32 to match size of target (4)" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 free.v(22) " "Warning: Verilog HDL assignment warning at free.v(22): truncated value with size 32 to match size of target (1)" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 free.v(23) " "Warning: Verilog HDL assignment warning at free.v(23): truncated value with size 32 to match size of target (4)" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 free.v(29) " "Warning: Verilog HDL assignment warning at free.v(29): truncated value with size 32 to match size of target (4)" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 29 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux3 mux3:mux " "Info: Elaborating entity \"mux3\" for hierarchy \"mux3:mux\"" {  } { { "hdlc.v" "mux" { Text "F:/my_design/hdlc/hdlc.v" 21 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dout mux3.v(11) " "Warning: Verilog HDL Always Construct warning at mux3.v(11): variable \"dout\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"dout\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "mux3.v" "" { Text "F:/my_design/hdlc/mux3.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control control:control1 " "Info: Elaborating entity \"control\" for hierarchy \"control:control1\"" {  } { { "hdlc.v" "control1" { Text "F:/my_design/hdlc/hdlc.v" 24 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "j control.v(8) " "Info: (10035) Verilog HDL or VHDL information at control.v(8): object \"j\" declared but not used" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 8 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(12) " "Warning: Verilog HDL assignment warning at control.v(12): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ept control.v(13) " "Warning: Verilog HDL Always Construct warning at control.v(13): variable \"ept\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(13) " "Warning: Verilog HDL assignment warning at control.v(13): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ept control.v(14) " "Warning: Verilog HDL Always Construct warning at control.v(14): variable \"ept\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(15) " "Warning: Verilog HDL assignment warning at control.v(15): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(16) " "Warning: Verilog HDL assignment warning at control.v(16): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 16 0 0 } }  } 0}