{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ept control.v(18) " "Warning: Verilog HDL Always Construct warning at control.v(18): variable \"ept\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(19) " "Warning: Verilog HDL assignment warning at control.v(19): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(20) " "Warning: Verilog HDL assignment warning at control.v(20): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(23) " "Warning: Verilog HDL assignment warning at control.v(23): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(24) " "Warning: Verilog HDL assignment warning at control.v(24): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "en1 control.v(9) " "Warning: Verilog HDL Always Construct warning at control.v(9): variable \"en1\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"en1\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 9 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "en3 control.v(9) " "Warning: Verilog HDL Always Construct warning at control.v(9): variable \"en3\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"en3\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 9 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(30) " "Warning: Verilog HDL assignment warning at control.v(30): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(31) " "Warning: Verilog HDL assignment warning at control.v(31): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(32) " "Warning: Verilog HDL assignment warning at control.v(32): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(33) " "Warning: Verilog HDL assignment warning at control.v(33): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 control.v(34) " "Warning: Verilog HDL assignment warning at control.v(34): truncated value with size 32 to match size of target (4)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(41) " "Warning: Verilog HDL assignment warning at control.v(41): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(42) " "Warning: Verilog HDL assignment warning at control.v(42): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 control.v(46) " "Warning: Verilog HDL assignment warning at control.v(46): truncated value with size 32 to match size of target (4)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 46 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(48) " "Warning: Verilog HDL assignment warning at control.v(48): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(50) " "Warning: Verilog HDL assignment warning at control.v(50): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(56) " "Warning: Verilog HDL assignment warning at control.v(56): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 control.v(59) " "Warning: Verilog HDL assignment warning at control.v(59): truncated value with size 32 to match size of target (6)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(61) " "Warning: Verilog HDL assignment warning at control.v(61): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 61 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 control.v(65) " "Warning: Verilog HDL assignment warning at control.v(65): truncated value with size 32 to match size of target (6)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 control.v(68) " "Warning: Verilog HDL assignment warning at control.v(68): truncated value with size 32 to match size of target (6)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 68 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(70) " "Warning: Verilog HDL assignment warning at control.v(70): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 70 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 control.v(85) " "Warning: Verilog HDL assignment warning at control.v(85): truncated value with size 32 to match size of target (4)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 control.v(87) " "Warning: Verilog HDL assignment warning at control.v(87): truncated value with size 32 to match size of target (1)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 87 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 control.v(88) " "Warning: Verilog HDL assignment warning at control.v(88): truncated value with size 32 to match size of target (4)" {  } { { "control.v" "" { Text "F:/my_design/hdlc/control.v" 88 0 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "free:free1\|d\[7\] High " "Info: Power-up level of register \"free:free1\|d\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[7\] data_in VCC " "Warning: Reduced register \"free:free1\|d\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[6\] data_in GND " "Warning: Reduced register \"free:free1\|d\[6\]\" with stuck data_in port to stuck value GND" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "free:free1\|d\[5\] High " "Info: Power-up level of register \"free:free1\|d\[5\]\" is not specified -- using power-up level of High to minimize register" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[5\] data_in VCC " "Warning: Reduced register \"free:free1\|d\[5\]\" with stuck data_in port to stuck value VCC" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[4\] data_in GND " "Warning: Reduced register \"free:free1\|d\[4\]\" with stuck data_in port to stuck value GND" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "free:free1\|d\[3\] High " "Info: Power-up level of register \"free:free1\|d\[3\]\" is not specified -- using power-up level of High to minimize register" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[3\] data_in VCC " "Warning: Reduced register \"free:free1\|d\[3\]\" with stuck data_in port to stuck value VCC" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "free:free1\|d\[2\] High " "Info: Power-up level of register \"free:free1\|d\[2\]\" is not specified -- using power-up level of High to minimize register" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[2\] data_in VCC " "Warning: Reduced register \"free:free1\|d\[2\]\" with stuck data_in port to stuck value VCC" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[1\] data_in GND " "Warning: Reduced register \"free:free1\|d\[1\]\" with stuck data_in port to stuck value GND" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "free:free1\|d\[0\] High " "Info: Power-up level of register \"free:free1\|d\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "free:free1\|d\[0\] data_in VCC " "Warning: Reduced register \"free:free1\|d\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "free.v" "" { Text "F:/my_design/hdlc/free.v" 12 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_jcc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_jcc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_jcc " "Info: Found entity 1: mux_jcc" {  } { { "db/mux_jcc.tdf" "" { Text "F:/my_design/hdlc/db/mux_jcc.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_2ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_2ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_2ec " "Info: Found entity 1: mux_2ec" {  } { { "db/mux_2ec.tdf" "" { Text "F:/my_design/hdlc/db/mux_2ec.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_3ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3ec " "Info: Found entity 1: mux_3ec" {  } { { "db/mux_3ec.tdf" "" { Text "F:/my_design/hdlc/db/mux_3ec.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 65 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 65 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 01 22:52:48 2007 " "Info: Processing ended: Sun Jul 01 22:52:48 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}