?? transfer.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity transfer is
port(clk,reset,start : in std_logic;
txd,txddone : out std_logic);
end transfer;
architecture behave of transfer is
component baud
port(clk,resetb : in std_logic;
bclk : out std_logic);
end component;
component txmit
port(bclkt,resett,xmit_cmd_p : in std_logic;
txd,txd_done : out std_logic);
end component;
signal bclk:std_logic;
begin
U1:baud port map ( clk , reset , bclk );
U2:txmit port map ( bclk, reset , start , txd, txddone );
end behave;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -