entity example_en_8bit_a is
      Port ( clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC;
             enable_in : In    STD_LOGIC;
             count_out : Out   STD_LOGIC_VECTOR (7 downto 0) );

   attribute syn_isclock: boolean;
 attribute syn_isclock of clk_in: signal is true;
end example_en_8bit_a;