?? example_en_8bit_a.srr
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===================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-------------------------------------------------------------------------
clear_in NA NA NA NA NA
clk_in NA NA NA NA NA
enable_in NA NA NA NA NA
=========================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-------------------------------------------------------------------------------------
count_out[0] System (rising) NA 0.000 1000.000 1000.000
count_out[1] System (rising) NA 0.000 1000.000 1000.000
count_out[2] System (rising) NA 0.000 1000.000 1000.000
count_out[3] System (rising) NA 0.000 1000.000 1000.000
count_out[4] System (rising) NA 0.000 1000.000 1000.000
count_out[5] System (rising) NA 0.000 1000.000 1000.000
count_out[6] System (rising) NA 0.000 1000.000 1000.000
count_out[7] System (rising) NA 0.000 1000.000 1000.000
=====================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
I6.I3.I2 System SUPER_LOGIC Q2Z count_reg[7] 0.000 1000.000
I6.I3.I2 System SUPER_LOGIC Q2Z count_reg[7] 0.000 1000.000
I6.I3.I2 System SUPER_LOGIC QZ count_reg[6] 0.000 1000.000
I6.I3.I2 System SUPER_LOGIC QZ count_reg[6] 0.000 1000.000
I6.I4.I2 System SUPER_LOGIC Q2Z count_reg[5] 0.000 1000.000
I6.I4.I2 System SUPER_LOGIC Q2Z count_reg[5] 0.000 1000.000
I6.I4.I2 System SUPER_LOGIC QZ count_reg[4] 0.000 1000.000
I6.I4.I2 System SUPER_LOGIC QZ count_reg[4] 0.000 1000.000
I6.I5.I2 System SUPER_LOGIC Q2Z count_reg[1] 0.000 1000.000
I6.I5.I2 System SUPER_LOGIC Q2Z count_reg[1] 0.000 1000.000
========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------
I8.I1 System OUTPAD_25UM A count_reg[0] 1000.000 1000.000
I8.I2 System OUTPAD_25UM A count_reg[1] 1000.000 1000.000
I8.I3 System OUTPAD_25UM A count_reg[2] 1000.000 1000.000
I8.I4 System OUTPAD_25UM A count_reg[3] 1000.000 1000.000
I8.I5 System OUTPAD_25UM A count_reg[4] 1000.000 1000.000
I8.I6 System OUTPAD_25UM A count_reg[5] 1000.000 1000.000
I8.I7 System OUTPAD_25UM A count_reg[6] 1000.000 1000.000
I8.I8 System OUTPAD_25UM A count_reg[7] 1000.000 1000.000
count_out[7:0] System Port count_out[0] count_out[0] 1000.000 1000.000
count_out[7:0] System Port count_out[1] count_out[1] 1000.000 1000.000
========================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.000
= Required time: 1000.000
- Propagation time: 0.000
= Slack (critical) : 1000.000
Number of logic level(s): 0
Starting point: I6.I3.I2 / Q2Z
Ending point: I8.I8 / A
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
I6.I3.I2 SUPER_LOGIC Q2Z Out 0.000 0.000 -
count_reg[7] Net - - - - 1
I8.I8 OUTPAD_25UM A In 0.000 0.000 -
====================================================================================
##### END OF TIMING REPORT #####]
Wrote QDIF file 'C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_8bit\example_en_8bit_a.qdf' part='ql8325' grade='-6' package='pq208'.
Mapper successful!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
###########################################################]
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