; Time: Wed Aug 18 16:50:56 2004
; SpDE Version: SpDE 9.6.2 Release Build3
; Time: Wed Aug 18 16:50:56 2004
; Status: Load file C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_8bit\example_en_8bit_a.qdf begin...
; Time: Wed Aug 18 16:50:58 2004
; Status: Load file C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_8bit\example_en_8bit_a.qdf complete
; Time: Wed Aug 18 16:50:58 2004
; Status: Fragment-Level Netlister begin...
; Time: Wed Aug 18 16:50:58 2004
; Status: Fragment-Level Netlister complete
; Time: Wed Aug 18 16:50:58 2004
; Status: Read constraint file example_en_8bit_a.qcf begin...
; Warning:  Module I12 not exists, it will be ignored 
; Time: Wed Aug 18 16:50:58 2004
; Status: Read constraint file example_en_8bit_a.qcf complete...
; Time: Wed Aug 18 16:50:58 2004
; Status: No ESP Configuration file loaded
; Time: Wed Aug 18 16:50:59 2004
; Status: Verifier begin...
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: buffer removal starts
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: buffer removal ends
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: const FFs removal starts
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: const FFs removal ends
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: begin fixing global clock buffers
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: finished fixing global clock buffers
; INote: Gate .clear_in_p is not used, and is being removed
; INote: Gate .enable_in_p is not used, and is being removed
;  Gate I11 is placed on the Dedicated Clock Pad
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: vrAddFF2Clock
; Time: Wed Aug 18 16:50:59 2004
; Status: verifier: vrAddFF2Clock
; Time: Wed Aug 18 16:50:59 2004
; Status: Verifier complete
; Time: Wed Aug 18 16:50:59 2004
; Status: Fragment-Level Netlister begin...
; Time: Wed Aug 18 16:50:59 2004
; Status: Fragment-Level Netlister complete
; Time: Wed Aug 18 16:51:06 2004
; Status: Saving file C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_8bit\example_en_8bit_a.chp
; Time: Wed Aug 18 16:51:06 2004
; Status: File C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_8bit\example_en_8bit_a.chp saved
; Options for logic optimizer
; logic optimizer.Mode = Quality
; logic optimizer.Goal = Speed
; logic optimizer.p2Level = 1
; logic optimizer.Level = 2
; logic optimizer.IgnorePack = FALSE
; logic optimizer.Utilization = 0
; logic optimizer.FragAUtilization = 0
; logic optimizer.FragFUtilization = 0
; logic optimizer.FragOUtilization = 0
; logic optimizer.FragNUtilization = 0
; logic optimizer.FragQUtilization = 0
; logic optimizer.FragQ2Utilization = 0
; logic optimizer.UseNonBondedPads = TRUE
; Time: Wed Aug 18 16:51:13 2004
; Status: Logic Optimizer begin: minimize delay.
; Time: Wed Aug 18 16:51:13 2004
; Status: Pulling 0 FFs into pads by user's specification.
; Time: Wed Aug 18 16:51:13 2004
; Status: Technology mapping...
; Time: Wed Aug 18 16:51:13 2004
; Status: Initializing AD with constraints ...
; Time: Wed Aug 18 16:51:13 2004
; Status: Timing driven calculations begin...
; Time: Wed Aug 18 16:51:13 2004
; Status: Timing driven calculations end...
; Time: Wed Aug 18 16:51:13 2004
; Status: No more logic to reoptimize.
; Time: Wed Aug 18 16:51:13 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:13 2004
; Status: Packing...
Total number of buffers = 0
; Time: Wed Aug 18 16:51:13 2004
; Result: ;Summary: Logic cell utilization: 0
; Time: Wed Aug 18 16:51:13 2004
; Result: ; Summary: IO control cells: 0 of 0
; Time: Wed Aug 18 16:51:13 2004
; Result: ; Summary: Clock-only cells: 1 of 9
; Time: Wed Aug 18 16:51:13 2004
; Result: ; Summary: Bi-directional cells: 8 of 115
; Time: Wed Aug 18 16:51:13 2004
; Status: Checking functionality
; Time: Wed Aug 18 16:51:13 2004
; Status: Logic Optimizer complete
; Options for placer
; placer.Seed = 42
; placer.Mode = Quality
; placer.Lambda = 0.300000
; placer.Level = 1
; placer.FastAnnealer = 2
; Time: Wed Aug 18 16:51:13 2004
; Status: Gclk Buffer Insertion Starts...
; Time: Wed Aug 18 16:51:13 2004
; Status: Gclk Buffer Insertion Ends...
; Time: Wed Aug 18 16:51:13 2004
; Status: Placer begin...
; Time: Wed Aug 18 16:51:13 2004
; Status: global placer begin...
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:14 2004
; Status: Initializing AD with constraints ...
; Time: Wed Aug 18 16:51:14 2004
; Status: FastPlacer running...
Debug: level=0  ,   bbCost=129.000000 
Debug: level=1  ,   bbCost=129.000000 
Debug: level=1  ,   bbCost=129.000000 
Debug: level=2  ,   bbCost=129.000000 
Debug: level=2  ,   bbCost=129.000000 
; Time: Wed Aug 18 16:51:14 2004
; Status: FastPlacer finished
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:14 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:14 2004
; Status: Placement Buffering
; Time: Wed Aug 18 16:51:14 2004
; Status: Post-placement optimization.
; Time: Wed Aug 18 16:51:14 2004
; Status: placement buffering starts.
; Time: Wed Aug 18 16:51:14 2004
; Status: Placement buffering complete -- 0 buffers inserted.
; Time: Wed Aug 18 16:51:14 2004
; Status: global placer complete
; Time: Wed Aug 18 16:51:14 2004
; Status: detail placer begin...
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:14 2004
; Status: Initializing AD with constraints ...
Power Reduction OFF
; Time: Wed Aug 18 16:51:14 2004
; Status: Finding initial temperature...
currentbCost = 43.000000
IntSearchTemp: temp= 10 costFactor= 0.000000 
IntSearchTemp: temp= 14 costFactor= 0.046512 
anLambda = 0.300, LCellUsageRatio = 0.0026
; Time: Wed Aug 18 16:51:14 2004
; Status: Cycle loop begin...
Debug: Temp 21.000000, rate 1.000000, Beta 0, cost 43, bbCost 49.000000, tdCost 0.996286, Cost 78.604949, sigma 0.020000
minAdjustCost = 48, power factor = 0.53
0 buffer tree adjusted
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:14 2004
; Status: AD Close...
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:15 2004
; Status: Initializing AD with constraints ...
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:15 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:15 2004
; Status: Post-placement optimization.
; Time: Wed Aug 18 16:51:15 2004
; Status: placement buffering starts.
; Time: Wed Aug 18 16:51:15 2004
; Status: Placement buffering complete -- 0 buffers inserted.
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:15 2004
; Status: Initializing AD with constraints ...
minAdjustCost = 43, power factor = 0.53
0 buffer tree adjusted
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:15 2004
; Status: AD Close...
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:15 2004
; Status: Initializing AD with constraints ...
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:15 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:15 2004
; Status: Post-placement optimization.
; Time: Wed Aug 18 16:51:15 2004
; Status: placement buffering starts.
; Time: Wed Aug 18 16:51:15 2004
; Status: Placement buffering complete -- 0 buffers inserted.
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:15 2004
; Status: Initializing AD with constraints ...
minAdjustCost = 39, power factor = 0.53
0 buffer tree adjusted
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:15 2004
; Status: AD Close...
Debug: Initializing Ad Module
; Time: Wed Aug 18 16:51:15 2004
; Status: Initializing AD with constraints ...
Debug: Temp 0.000000, rate 0.009231, Beta 25.6524, cost 40, bbCost 40.000000, tdCost 2.037493, Cost 92.266490, sigma 0.020000
; Time: Wed Aug 18 16:51:15 2004
; Status: Cycle loop with 14625 attempted moves complete
minAdjustCost = 37, power factor = 0.53
0 buffer tree adjusted
Debug: Closing Ad-Module
; Time: Wed Aug 18 16:51:16 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:16 2004
; Status: detail placer complete
; Time: Wed Aug 18 16:51:16 2004
; Status: Placer complete
; Time: Wed Aug 18 16:51:16 2004
; Status: Gclk Buffer Insertion Starts...
; Time: Wed Aug 18 16:51:16 2004
; Status: Gclk Buffer Insertion Ends...
; Time: Wed Aug 18 16:51:16 2004
; Status: Post-placement optimization.
; Time: Wed Aug 18 16:51:16 2004
; Status: Auto buffering starts.
; Time: Wed Aug 18 16:51:16 2004
; Result: ;Summary: Logic cell utilization: 0
; Time: Wed Aug 18 16:51:16 2004
; Result: ; Summary: IO control cells: 0 of 0
; Time: Wed Aug 18 16:51:16 2004
; Result: ; Summary: Clock-only cells: 1 of 9
; Time: Wed Aug 18 16:51:16 2004
; Result: ; Summary: Bi-directional cells: 8 of 115
; Time: Wed Aug 18 16:51:16 2004
; Status: Auto buffering complete -- 0 buffers inserted.
; Time: Wed Aug 18 16:51:16 2004
; Status: Global router begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: initializing...
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment-Level Netlister begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment-Level Netlister complete
; Time: Wed Aug 18 16:51:16 2004
; Status: Initializing AD with constraints ...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: beginning initial cycle
; Time: Wed Aug 18 16:51:16 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2 Global router complete.
; Time: Wed Aug 18 16:51:16 2004
; Status: Layout Based optimization.
; Time: Wed Aug 18 16:51:16 2004
; Status: Initializing AD with constraints ...
; Time: Wed Aug 18 16:51:16 2004
; Status: Timing driven calculations begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: Timing driven calculations end...
; Time: Wed Aug 18 16:51:16 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:16 2004
; Status: Post Layout buffering complete -- 0 buffers inserted.
; Time: Wed Aug 18 16:51:16 2004
; Status: Fixing bypass muxes starts.
; Time: Wed Aug 18 16:51:16 2004
; Status: Fixing bypass muxes--0 bypass muxes, 0 swaps.
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment-Level Netlister begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment-Level Netlister complete
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment simulator begins ...
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment simulator ends successfully.
; Options for router
; router.MinCycles = 5
; router.MaxCycles = 512
; router.Seed = 42
; router.LoopCnt = 5
; router.MaxHidriveFanouts = 20
; router.CongestionTable = 0
; router.RouteMode = 0
; router.PureMagic = 0
; router.NetMagic = 0
; router.UnusedIO = 0
; Time: Wed Aug 18 16:51:16 2004
; Status: R2 router begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: routing clock nets
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: routing supply nets
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: initializing...
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment-Level Netlister begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: Fragment-Level Netlister complete
; Time: Wed Aug 18 16:51:16 2004
; Status: Initializing AD with constraints ...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: routing low skew nets
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: routing conventional nets...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: beginning initial cycle
Debug: cycle= 0: cong= 0  over= 0  histoc= 0
Debug: cycle= 0: overconstraints= 0
; Time: Wed Aug 18 16:51:16 2004
; Status: Timing driven calculations begin...
; Time: Wed Aug 18 16:51:16 2004
; Status: Timing driven calculations end...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: detail routing...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2: writeback...
; Time: Wed Aug 18 16:51:16 2004
; Status: AD Close...
; Time: Wed Aug 18 16:51:16 2004
; Status: R2 router complete.
; Options for delay modeler
; delay modeler.Mode = Commercial
; delay modeler.Corner = Worst
; delay modeler.OutPadCap = 30.000000
; delay modeler.SpeedGrade = 6
; delay modeler.LowPower = FALSE
; delay modeler.CustomVccBest = 1.800000
; delay modeler.CustomVccNominal = 1.800000
; delay modeler.CustomVccWorst = 1.800000
; delay modeler.CustomVccLPBest = 3.600000
; delay modeler.CustomVccLPNominal = 3.300000
; delay modeler.CustomVccLPWorst = 3.000000
; delay modeler.CustomTempBest = 25.000000
; delay modeler.CustomTempNominal = 25.000000
; delay modeler.CustomTempWorst = 25.000000
; Time: Wed Aug 18 16:51:17 2004
; Status: Delay Simulator begin...
; Time: Wed Aug 18 16:51:17 2004
; Status: Delay Simulator complete
; Options for back annotation
; Time: Wed Aug 18 16:51:17 2004
; Status: Verilog back annotation begin...
; Time: Wed Aug 18 16:51:17 2004
; Status: Verilog netlist begin...
; Time: Wed Aug 18 16:51:17 2004
; Status: Verilog back annotation in progress...
; Time: Wed Aug 18 16:51:17 2004
; Status: Verilog netlist complete
; Time: Wed Aug 18 16:51:17 2004
; Status: SDF back annotation begin...
; Time: Wed Aug 18 16:51:17 2004
; Status: SDF back annotation complete
; Time: Wed Aug 18 16:51:17 2004
; Status: Verilog back annotation complete
; Time: Wed Aug 18 16:51:17 2004
; Status: Back annotation begin...
; Time: Wed Aug 18 16:51:17 2004
; Status: Back annotation complete
; Time: Wed Aug 18 16:51:21 2004
; Status: Report file C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_8bit\example_en_8bit_a_rpt.html created.
Debug: Synplicity run options: C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_16bit\example_en_16bit_a.prj