?? example_en_8bit_a.chp

?? VHDL examples for counter design, use QuickLogic eclips
?? CHP
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# Created by SPDE version SpDE 9.6.2 Release Build3 on Wed Aug 18 16:51:06 2004
# SpDE built Jun 28 2004 12:15:01
# Device file compiled on Wed Jun 02 11:11:32 2004
QDIF 5
file ql8325
package PQ208
tools
  partdef 9400
  design 3000
  verifier 9600
    option Strip boolean true
    option RemoveBuffersOnLoad boolean true
    option RemoveConstFFs boolean true
    option FixGlobalClks boolean true
    option IgnorePackOnBuffers boolean true
end
library QDIF
  gates 18
  terms 454
  ports 557
  gate Q_INPAD_25UM cell BIDIR
    term GND port EQE port IE port IQC port IQE port IQR end
    term VCC port ESEL port OQI port OSEL end
    term Q port IZ end
    term P port IP end
  end
  gate CKPAD_25UM cell CLOCK
    term Q port IC end
    term P port IP end
  end
  gate OUTPAD_25UM cell BIDIR
    term SLEWRATE port SLEWRATE end
    term WPD port WPD end
    term ISEL port ISEL end
    term GND port IQR port IQE port IQC end
    term VCC port OSEL port IE port ESEL port EQE end
    term P port IP end
    term A port OQI end
  end
  gate SUPER_LOGIC cell LOGIC
    term DCLK port DCLK end
    term CLKSEL port CLKSEL end
    term QZ port QZ end
    term Q2Z port Q2Z end
    term OZ port OZ end
    term NZ port NZ end
    term FZ port FZ end
    term AZ port AZ end
    term QS port QS end
    term QR port QR end
    term QC port QC end
    term PS port PS end
    term PP port PP end
    term OS port OS end
    term OP port OP end
    term NS port NS end
    term NP port NP end
    term MS port MS end
    term MP port MP end
    term F6 port F6 end
    term F5 port F5 end
    term F4 port F4 end
    term F3 port F3 end
    term F2 port F2 end
    term F1 port F1 end
    term E2 port E2 end
    term E1 port E1 end
    term D2 port D2 end
    term D1 port D1 end
    term C2 port C2 end
    term C1 port C1 end
    term B2 port B2 end
    term B1 port B1 end
    term A6 port A6 end
    term A5 port A5 end
    term A4 port A4 end
    term A3 port A3 end
    term A2 port A2 end
    term A1 port A1 end
  end
  gate RAM256X4 cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[7] port WA7 end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[7] port RA7 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[3] port WD13 end
    term WD[2] port WD9 end
    term WD[1] port WD4 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[3] port RD13 end
    term RD[2] port RD9 end
    term RD[1] port RD4 end
    term RD[0] port RD0 end
    term GND port WA8 port RA8 port WD17 port WD16 port WD15 port WD14 port WD12 port WD11 port WD10 port WD8 port WD7 port WD6 port WD5 port WD3 port WD2 port WD1 port MODE0 end
    term VCC port MODE1 end
  end
  gate RAM512X2 cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[8] port WA8 end
    term WA[7] port WA7 end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[8] port RA8 end
    term RA[7] port RA7 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[1] port WD9 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[1] port RD9 end
    term RD[0] port RD0 end
    term GND port WD17 port WD16 port WD15 port WD14 port WD13 port WD12 port WD11 port WD10 port WD8 port WD7 port WD6 port WD5 port WD4 port WD3 port WD2 port WD1 end
    term VCC port MODE1 port MODE0 end
  end
  gate RAM128X9 cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[8] port WD17 end
    term WD[7] port WD15 end
    term WD[6] port WD13 end
    term WD[5] port WD11 end
    term WD[4] port WD9 end
    term WD[3] port WD6 end
    term WD[2] port WD4 end
    term WD[1] port WD2 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[8] port RD17 end
    term RD[7] port RD15 end
    term RD[6] port RD13 end
    term RD[5] port RD11 end
    term RD[4] port RD9 end
    term RD[3] port RD6 end
    term RD[2] port RD4 end
    term RD[1] port RD2 end
    term RD[0] port RD0 end
    term GND port WA8 port WA7 port RA8 port RA7 port WD16 port WD14 port WD12 port WD10 port WD8 port WD7 port WD5 port WD3 port WD1 port MODE1 end
    term VCC port MODE0 end
  end
  gate RAM64X18 cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[17] port WD17 end
    term WD[16] port WD16 end
    term WD[15] port WD15 end
    term WD[14] port WD14 end
    term WD[13] port WD13 end
    term WD[12] port WD12 end
    term WD[11] port WD11 end
    term WD[10] port WD10 end
    term WD[9] port WD9 end
    term WD[8] port WD8 end
    term WD[7] port WD7 end
    term WD[6] port WD6 end
    term WD[5] port WD5 end
    term WD[4] port WD4 end
    term WD[3] port WD3 end
    term WD[2] port WD2 end
    term WD[1] port WD1 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[17] port RD17 end
    term RD[16] port RD16 end
    term RD[15] port RD15 end
    term RD[14] port RD14 end
    term RD[13] port RD13 end
    term RD[12] port RD12 end
    term RD[11] port RD11 end
    term RD[10] port RD10 end
    term RD[9] port RD9 end
    term RD[8] port RD8 end
    term RD[7] port RD7 end
    term RD[6] port RD6 end
    term RD[5] port RD5 end
    term RD[4] port RD4 end
    term RD[3] port RD3 end
    term RD[2] port RD2 end
    term RD[1] port RD1 end
    term RD[0] port RD0 end
    term GND port WA8 port WA7 port WA6 port RA8 port RA7 port RA6 port MODE1 port MODE0 end
    term VCC end
  end
  gate RAM512X4_25UM cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[8] port WA8 end
    term WA[7] port WA7 end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[8] port RA8 end
    term RA[7] port RA7 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[3] port WD13 end
    term WD[2] port WD9 end
    term WD[1] port WD4 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[3] port RD13 end
    term RD[2] port RD9 end
    term RD[1] port RD4 end
    term RD[0] port RD0 end
    term GND port WA9 port RA9 port WD17 port WD16 port WD15 port WD14 port WD12 port WD11 port WD10 port WD8 port WD7 port WD6 port WD5 port WD3 port WD2 port WD1 port MODE0 end
    term VCC port MODE1 end
  end
  gate RAM1024X2_25UM cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[9] port WA9 end
    term WA[8] port WA8 end
    term WA[7] port WA7 end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[9] port RA9 end
    term RA[8] port RA8 end
    term RA[7] port RA7 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[1] port WD9 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[1] port RD9 end
    term RD[0] port RD0 end
    term GND port WD17 port WD16 port WD15 port WD14 port WD13 port WD12 port WD11 port WD10 port WD8 port WD7 port WD6 port WD5 port WD4 port WD3 port WD2 port WD1 end
    term VCC port MODE1 port MODE0 end
  end
  gate RAM256X9_25UM cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[7] port WA7 end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[7] port RA7 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[8] port WD17 end
    term WD[7] port WD15 end
    term WD[6] port WD13 end
    term WD[5] port WD11 end
    term WD[4] port WD9 end
    term WD[3] port WD6 end
    term WD[2] port WD4 end
    term WD[1] port WD2 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[8] port RD17 end
    term RD[7] port RD15 end
    term RD[6] port RD13 end
    term RD[5] port RD11 end
    term RD[4] port RD9 end
    term RD[3] port RD6 end
    term RD[2] port RD4 end
    term RD[1] port RD2 end
    term RD[0] port RD0 end
    term GND port WA9 port WA8 port RA9 port RA8 port WD16 port WD14 port WD12 port WD10 port WD8 port WD7 port WD5 port WD3 port WD1 port MODE1 end
    term VCC port MODE0 end
  end
  gate RAM128X18_25UM cell RAM
    term WE port WE end
    term RE port RE end
    term WCLK port WCLK end
    term RCLK port RCLK end
    term WA[6] port WA6 end
    term WA[5] port WA5 end
    term WA[4] port WA4 end
    term WA[3] port WA3 end
    term WA[2] port WA2 end
    term WA[1] port WA1 end
    term WA[0] port WA0 end
    term RA[6] port RA6 end
    term RA[5] port RA5 end
    term RA[4] port RA4 end
    term RA[3] port RA3 end
    term RA[2] port RA2 end
    term RA[1] port RA1 end
    term RA[0] port RA0 end
    term WD[17] port WD17 end
    term WD[16] port WD16 end
    term WD[15] port WD15 end
    term WD[14] port WD14 end
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?? 文件大小 1269 K
?? 上傳用戶 zhang8818200
?? 所屬分類 VHDL/FPGA/Verilog
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?? example_en_8bit_a.chp

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