?? example_en_8bit_a.v

?? VHDL examples for counter design, use QuickLogic eclips
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/* Verilog Model Created from SCS Schematic example_en_8bit_a.sch 
   Aug 18, 2004 16:49 */

/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
	`ifdef synthesis
	`else
	`define synthesis
	`endif
`endif

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_en_8bit_a( clear_in , clk_in, enable_in, count_out );
input clear_in;
input clk_in /* synthesis syn_isclock=1 */;
//exemplar attribute clk_in syn_isclock true
 output [7:0] count_out;
input enable_in;
// exemplar attribute example_en_8bit_a dont_touch true 
parameter syn_macro = 1;
wire [7:0] count;
wire [7:0] count_reg;
wire enable_reg;
wire enable;
wire clk;
wire clear;

counter_en_8bit_a I12 ( .clear(enable_reg), .clk(clk), .enable(clear) );
rg8_25um I6 ( .CLK(clk), .D({ count[7:0] }), .Q({ count_reg[7:0] }) );
dff_2 I7 ( .CLK(clk), .D1(enable), .D2(enable), .Q1(enable_reg) );
opad8_25um I8 ( .A({ count_reg[7:0] }), .P({ count_out[7:0] }) );
inpad_25um I9 ( .P(enable_in), .Q(enable) );
ckpad_25um I10 ( .P(clear_in), .Q(clear) );
ckpad_25um I11 ( .P(clk_in), .Q(clk) );

endmodule // example_en_8bit_a


`ifdef counter_en_8bit_a
`else
`define counter_en_8bit_a
module counter_en_8bit_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
 output [7:0] count;
input enable;
// exemplar attribute counter_en_8bit_a dont_touch true 
parameter syn_macro = 1;
wire enable_8bit;

counter_en_h4bit I4 ( .clear(clear), .clk(clk), .enable(enable),
                   .enablehbit_a(enable_8bit), .qa_r(count[3]),
                   .qb_r(count[2]), .qc_r(count[1]), .qd_r(count[0]) );
counter_en_4bit I1 ( .clear(clear), .clk(clk), .enable(enable_8bit),
                  .qa_r(count[7]), .qb_r(count[6]), .qc_r(count[5]),
                  .qd_r(count[4]) );

endmodule // counter_en_8bit_a

`endif

`ifdef rg8_25um
`else
`define rg8_25um
module rg8_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
 input [7:0] D;
 output [7:0] Q;
// exemplar attribute rg8_25um dont_touch true 
parameter syn_macro = 1;

dff_2 I3 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I4 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
dff_2 I6 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );

endmodule // rg8_25um

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
input D1, D2;
output Q1, Q2;
// exemplar attribute dff_2 dont_touch true 
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1), .AZ(), .FZ(), .NZ(), .OZ() );

endmodule // dff_2

`endif

`ifdef opad8_25um
`else
`define opad8_25um
module opad8_25um( A , P );
 input [7:0] A;
 output [7:0] P;
// exemplar attribute opad8_25um dont_touch true 
parameter syn_macro = 1;

outpad_25um I1 ( .A(A[0]), .P(P[0]) );
outpad_25um I2 ( .A(A[1]), .P(P[1]) );
outpad_25um I3 ( .A(A[2]), .P(P[2]) );
outpad_25um I4 ( .A(A[3]), .P(P[3]) );
outpad_25um I5 ( .A(A[4]), .P(P[4]) );
outpad_25um I6 ( .A(A[5]), .P(P[5]) );
outpad_25um I7 ( .A(A[6]), .P(P[6]) );
outpad_25um I8 ( .A(A[7]), .P(P[7]) );

endmodule // opad8_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
// exemplar attribute inpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P /* synthesis syn_isclock=1 */;
//exemplar attribute P syn_isclock true
output Q;
// exemplar attribute ckpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef counter_en_h4bit
`else
`define counter_en_h4bit
module counter_en_h4bit( clear , clk, enable, enablehbit_a, qa_r, qb_r, qc_r, qd_r );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
input enable;
output enablehbit_a, qa_r, qb_r, qc_r, qd_r;
// exemplar attribute counter_en_h4bit dont_touch true 
parameter syn_macro = 1;
wire ED_a;
wire BCD_a;
supply0 GND;
supply1 VCC;

super_logic I1 ( .A1(BCD_a), .A2(GND), .A3(ED_a), .A4(GND), .A5(qa_r), .A6(GND),
              .AZ(enablehbit_a), .B1(ED_a), .B2(qc_r), .C1(qc_r), .C2(ED_a),
              .D1(qb_r), .D2(GND), .E1(VCC), .E2(qb_r), .F1(enable), .F2(GND),
              .F3(qd_r), .F4(GND), .F5(VCC), .F6(GND), .FZ(ED_a), .MP(GND),
              .MS(qc_r), .NP(qc_r), .NS(GND), .OP(GND), .OS(GND), .PP(GND),
              .PS(GND), .Q2Z(qb_r), .QC(clk), .QR(clear), .QS(GND), .QZ(qc_r), .NZ(), .OZ() );
super_logic I2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND),
              .B1(qa_r), .B2(GND), .C1(VCC), .C2(qa_r), .D1(enable), .D2(qd_r),
              .E1(qd_r), .E2(enable), .F1(qb_r), .F2(GND), .F3(qc_r), .F4(GND),
              .F5(qd_r), .F6(GND), .FZ(BCD_a), .MP(enable), .MS(GND), .NP(GND),
              .NS(qd_r), .OP(GND), .OS(GND), .PP(GND), .PS(GND), .Q2Z(qd_r),
              .QC(clk), .QR(clear), .QS(GND), .QZ(qa_r), .AZ(), .NZ(), .OZ() );

endmodule // counter_en_h4bit

`endif

`ifdef counter_en_4bit
`else
`define counter_en_4bit
module counter_en_4bit( clear , clk, enable, qa_r, qb_r, qc_r, qd_r );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
input enable;
output qa_r, qb_r, qc_r, qd_r;
// exemplar attribute counter_en_4bit dont_touch true 
parameter syn_macro = 1;
wire ED_a;
wire ABCDE_a;
wire BCD_a;
supply0 GND;
supply1 VCC;

super_logic I1 ( .A1(BCD_a), .A2(GND), .A3(ED_a), .A4(GND), .A5(qa_r), .A6(GND),
              .AZ(ABCDE_a), .B1(ED_a), .B2(qc_r), .C1(qc_r), .C2(ED_a),
              .D1(qb_r), .D2(GND), .E1(VCC), .E2(qb_r), .F1(enable), .F2(GND),
              .F3(qd_r), .F4(GND), .F5(VCC), .F6(GND), .FZ(ED_a), .MP(GND),
              .MS(qc_r), .NP(qc_r), .NS(GND), .OP(GND), .OS(GND), .PP(GND),
              .PS(GND), .Q2Z(qb_r), .QC(clk), .QR(clear), .QS(GND), .QZ(qc_r), .NZ(), .OZ() );
super_logic I2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND),
              .B1(qa_r), .B2(GND), .C1(VCC), .C2(qa_r), .D1(enable), .D2(qd_r),
              .E1(qd_r), .E2(enable), .F1(qb_r), .F2(GND), .F3(qc_r), .F4(GND),
              .F5(qd_r), .F6(GND), .FZ(BCD_a), .MP(enable), .MS(GND), .NP(GND),
              .NS(qd_r), .OP(GND), .OS(GND), .PP(GND), .PS(GND), .Q2Z(qd_r),
              .QC(clk), .QR(clear), .QS(GND), .QZ(qa_r), .AZ(), .NZ(), .OZ() );

endmodule // counter_en_4bit

`endif

`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                    F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
                    QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC /* synthesis syn_isclock=1 */;
//exemplar attribute QC syn_isclock true
input QR, QS;
output QZ;
// exemplar attribute super_logic dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `LOGIC;

super_cell I2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ),
             .B1(B1), .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1),
             .E2(E2), .F1(F1), .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6),
             .FZ(FZ), .MP(MP), .MS(MS), .NP(NP), .NS(NS), .NZ(NZ), .OP(OP),
             .OS(OS), .OZ(OZ), .PP(PP), .PS(PS), .Q2Z(Q2Z), .QC(QC), .QR(QR),
             .QS(QS), .QZ(QZ) );

endmodule // super_logic

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
// exemplar attribute outpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute eio_cell noopt true 
 wire EQMUX_Z, OQMUX_Z;  
 reg EQZ, OQQ, IQQ;  
 assign #1 EQMUX_Z = ESEL ? IE : EQZ;  
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ;  
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz;  
 assign #1 IZ = IP;  
 
`ifdef synthesis  
  always @ (posedge IQC or posedge IQR)  
    if (IQR) 
      #1 EQZ = 1'b0; 
    else if (EQE) 
      #1 EQZ = IE;  
  always @ (posedge IQC or posedge IQR)  
    if (IQR) 
      #1 IQQ = 1'b0;  
    else if (IQE)  
      #1 IQQ = IP;  
  always @ (posedge IQC or posedge IQR)  
    if (IQR)  
      #1 OQQ = 1'b0;  
    else  
      #1 OQQ = OQI;  
`else  
/* synopsys translate_off */
  always @ (posedge IQC)  
    if (~IQR & EQE) 
      #1 EQZ = IE;  
    else if (IQR)  
      #1 EQZ = 1'b0; 
  always @ (posedge IQC)  
    if (~IQR & IQE)  
      #1 IQQ = IP;  
    else if (IQR)  
      #1 IQQ = 1'b0;  always @ (posedge IQC)  
    if (~IQR)  
      #1 OQQ = OQI;  
    else if (IQR)  
      #1 OQQ = 1'b0;  
/* synopsys translate_on */
`endif  
 

endmodule // eio_cell

`endif

`ifdef ckcell_25um
`else
`define ckcell_25um
module ckcell_25um( IP , IC );
output IC;
input IP;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute ckcell_25um noopt true 
 assign #1 IC = IP;

endmodule // ckcell_25um

`endif

`ifdef super_cell
`else
`define super_cell
module super_cell( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                   F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC, QR,
                   QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute super_cell noopt true 
 wire TOPMUX_Z, MIDMUX_Z, BOTMUX_Z, FFMUX_Z, CLKMUX_Z; 
 wire MZ; 
 reg QZ, Q2Z; 
 
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6; 
 assign #1 TOPMUX_Z = OP ? AZ : OS; 
 assign #1 MZ = MIDMUX_Z ? (C1 & ~C2) : (B1 & ~B2); 
 assign #1 MIDMUX_Z = MP ? FZ : MS; 
 assign #1 NZ = BOTMUX_Z ? (E1 & ~E2) : (D1 & ~D2); 
 assign #1 BOTMUX_Z = NP ? FZ : NS; 
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6; 
 assign #1 OZ = TOPMUX_Z ? NZ : MZ; 
 assign #1 FFMUX_Z = PP ? PS : NZ; 
`ifdef synthesis 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
     else 
        #1 QZ = OZ; 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
     else 
        #1 Q2Z = FFMUX_Z; 
`else 
/* synopsys translate_off */
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 QZ = OZ; 
  always @ (QR or QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 Q2Z = FFMUX_Z; 
  always @ (QR or QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
/* synopsys translate_on */
`endif 

endmodule // super_cell

`endif
?? 文件大小 1269 K
?? 上傳用戶 zhang8818200
?? 所屬分類 VHDL/FPGA/Verilog
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?? example_en_8bit_a.v

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