-- VHDL Model Created from SCS Schematic example_en_4bit.sch 
-- Aug 13, 2003 12:31 

-- Automatically generated by vdvhdl version 9.5 Release Build2 

library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_4BIT_S is
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
              enable : In    STD_LOGIC;
             enablehbit_a : Out   STD_LOGIC;
                qa_r : Out   STD_LOGIC;
                qb_r : Out   STD_LOGIC;
                qc_r : Out   STD_LOGIC;
                qd_r : Out   STD_LOGIC );
end COUNTER_EN_4BIT_S;


architecture SCHEMATIC of COUNTER_EN_4BIT_S is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal     ED_a : STD_LOGIC;
   signal    BCD_a : STD_LOGIC;
	constant 		GND : STD_LOGIC := '0';
	constant 		VCC : STD_LOGIC := '1';
   signal enablehbit_a_DUMMY : STD_LOGIC;
   signal qa_r_DUMMY : STD_LOGIC;
   signal qb_r_DUMMY : STD_LOGIC;
   signal qc_r_DUMMY : STD_LOGIC;
   signal qd_r_DUMMY : STD_LOGIC;

   component SUPER_LOGIC
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                  F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  MP : In    STD_LOGIC;
                  MS : In    STD_LOGIC;
                  NP : In    STD_LOGIC;
                \NS\ : In    STD_LOGIC;
                  OP : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  PP : In    STD_LOGIC;
                  PS : In    STD_LOGIC;
                  QC : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC;
                  FZ : Out   STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC;
                 Q2Z : Out   STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

begin


   enablehbit_a <= enablehbit_a_DUMMY;
   qa_r <= qa_r_DUMMY;
   qb_r <= qb_r_DUMMY;
   qc_r <= qc_r_DUMMY;
   qd_r <= qd_r_DUMMY;
   I1 : SUPER_LOGIC
      Port Map ( A1=>BCD_a, A2=>GND, A3=>ED_a, A4=>GND, A5=>qa_r_DUMMY,
                 A6=>GND, B1=>ED_a, B2=>qc_r_DUMMY, C1=>qc_r_DUMMY,
                 C2=>ED_a, D1=>qb_r_DUMMY, D2=>GND, E1=>VCC,
                 E2=>qb_r_DUMMY, F1=>enable, F2=>GND, F3=>qd_r_DUMMY,
                 F4=>GND, F5=>VCC, F6=>GND, MP=>GND, MS=>qc_r_DUMMY,
                 NP=>qc_r_DUMMY, \NS\=>GND, OP=>GND, OS=>GND, PP=>GND,
                 PS=>GND, QC=>clk, QR=>clear, QS=>GND,
                 AZ=>enablehbit_a_DUMMY, FZ=>ED_a, NZ=>open, OZ=>open,
                 Q2Z=>qb_r_DUMMY, QZ=>qc_r_DUMMY );
   I2 : SUPER_LOGIC
      Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
                 B1=>qa_r_DUMMY, B2=>GND, C1=>VCC, C2=>qa_r_DUMMY,
                 D1=>enable, D2=>qd_r_DUMMY, E1=>qd_r_DUMMY, E2=>enable,
                 F1=>qb_r_DUMMY, F2=>GND, F3=>qc_r_DUMMY, F4=>GND,
                 F5=>qd_r_DUMMY, F6=>GND, MP=>enable, MS=>GND, NP=>GND,
                 \NS\=>qd_r_DUMMY, OP=>GND, OS=>GND, PP=>GND, PS=>GND,
                 QC=>clk, QR=>clear, QS=>GND, AZ=>open, FZ=>BCD_a,
                 NZ=>open, OZ=>open, Q2Z=>qd_r_DUMMY, QZ=>qa_r_DUMMY );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
entity example_en_4bit is
      Port ( count_out : Out   STD_LOGIC_VECTOR (3 downto 0);
             enable_in : In    STD_LOGIC;
             clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC );
end example_en_4bit;


architecture SCHEMATIC of example_en_4bit is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal count_reg : STD_LOGIC_VECTOR (3 downto 0);
   signal    count : STD_LOGIC_VECTOR (3 downto 0);
   signal enable_reg : STD_LOGIC;
   signal   enable : STD_LOGIC;
   signal    clear : STD_LOGIC;
   signal      clk : STD_LOGIC;
   signal count_out_DUMMY : STD_LOGIC_VECTOR  (3 downto 0);

   component COUNTER_EN_4BIT_S
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
              enable : In    STD_LOGIC;
             enablehbit_a : Out   STD_LOGIC;
                qa_r : Out   STD_LOGIC;
                qb_r : Out   STD_LOGIC;
                qc_r : Out   STD_LOGIC;
                qd_r : Out   STD_LOGIC );
   end component;

   component RG4
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (3 downto 0);
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

   component DFF_2
      Port (     CLK : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  Q1 : Out   STD_LOGIC;
                  Q2 : Out   STD_LOGIC );
   end component;

   component OPAD4_25UM
      Port (       A : In    STD_LOGIC_VECTOR  (3 downto 0);
                   P : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

   component INPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component CKPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   count_out(3 downto 0) <= count_out_DUMMY(3 downto 0);
   I11 : COUNTER_EN_4BIT_S
      Port Map ( clear=>clear, clk=>clk, enable=>enable_reg,
                 enablehbit_a=>open, qa_r=>count(3), qb_r=>count(2),
                 qc_r=>count(1), qd_r=>count(0) );
   I9 : RG4
      Port Map ( CLK=>clk, D(3 downto 0)=>count(3 downto 0),
                 Q(3 downto 0)=>count_reg(3 downto 0) );
   I10 : DFF_2
      Port Map ( CLK=>clk, D1=>enable, D2=>enable, Q1=>enable_reg,
                 Q2=>open );
   I5 : OPAD4_25UM
      Port Map ( A(3 downto 0)=>count_reg(3 downto 0),
                 P(3 downto 0)=>count_out_DUMMY(3 downto 0) );
   I6 : INPAD_25UM
      Port Map ( P=>enable_in, Q=>enable );
   I7 : CKPAD_25UM
      Port Map ( P=>clk_in, Q=>clk );
   I8 : CKPAD_25UM
      Port Map ( P=>clear_in, Q=>clear );

end SCHEMATIC;