?? example_en_16bit_a.vhd
字號:
Port Map ( clear=>clear, clk=>clk, enable=>enable_8bit,
qa_r=>count_DUMMY(7), qb_r=>count_DUMMY(6),
qc_r=>count_DUMMY(5), qd_r=>count_DUMMY(4) );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_8BIT_A_I is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
en_8bit_a : Out STD_LOGIC );
attribute syn_isclock: boolean;
attribute syn_isclock of clk: signal is true;
end COUNTER_EN_8BIT_A_I;
architecture SCHEMATIC of COUNTER_EN_8BIT_A_I is
attribute syn_macro : integer;
attribute dont_touch : boolean;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute dont_touch of SCHEMATIC : architecture is TRUE;
signal en_8bit3_a : STD_LOGIC;
signal en_8bit2_a : STD_LOGIC;
signal en_8bit1_a : STD_LOGIC;
signal enableh4bit : STD_LOGIC;
constant VCC : STD_LOGIC := '1';
constant GND : STD_LOGIC := '0';
signal count_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
signal en_8bit_a_DUMMY : STD_LOGIC;
component COUNTER_EN_H4BIT
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
enablehbit_a : Out STD_LOGIC;
qa_r : Out STD_LOGIC;
qb_r : Out STD_LOGIC;
qc_r : Out STD_LOGIC;
qd_r : Out STD_LOGIC );
end component;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
count(7 downto 0) <= count_DUMMY(7 downto 0);
en_8bit_a <= en_8bit_a_DUMMY;
I8 : COUNTER_EN_H4BIT
Port Map ( clear=>clear, clk=>clk, enable=>enable,
enablehbit_a=>enableh4bit, qa_r=>count_DUMMY(3),
qb_r=>count_DUMMY(2), qc_r=>count_DUMMY(1),
qd_r=>count_DUMMY(0) );
I7 : COUNTER_EN_H4BIT
Port Map ( clear=>clear, clk=>clk, enable=>enableh4bit,
enablehbit_a=>open, qa_r=>count_DUMMY(7),
qb_r=>count_DUMMY(6), qc_r=>count_DUMMY(5),
qd_r=>count_DUMMY(4) );
I1 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(0), A2=>gnd, A3=>count_DUMMY(1),
A4=>gnd, A5=>count_DUMMY(2), A6=>gnd, B1=>vcc, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>vcc, D2=>gnd, E1=>vcc, E2=>gnd,
F1=>count_DUMMY(6), F2=>gnd, F3=>count_DUMMY(7),
F4=>gnd, F5=>enable, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd,
\NS\=>gnd, OP=>gnd, OS=>gnd, PP=>gnd, PS=>gnd, QC=>gnd,
QR=>gnd, QS=>gnd, AZ=>en_8bit1_a, FZ=>en_8bit2_a,
NZ=>open, OZ=>open, Q2Z=>open, QZ=>open );
I2 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(4),
A4=>gnd, A5=>count_DUMMY(5), A6=>gnd, B1=>vcc, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>vcc, D2=>gnd, E1=>vcc, E2=>gnd,
F1=>en_8bit1_a, F2=>gnd, F3=>en_8bit2_a, F4=>gnd,
F5=>en_8bit3_a, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd,
\NS\=>gnd, OP=>gnd, OS=>gnd, PP=>gnd, PS=>gnd, QC=>gnd,
QR=>gnd, QS=>gnd, AZ=>en_8bit3_a, FZ=>en_8bit_a_DUMMY,
NZ=>open, OZ=>open, Q2Z=>open, QZ=>open );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_16BIT_A is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (15 downto 0) );
attribute syn_isclock: boolean;
attribute syn_isclock of clk: signal is true;
end COUNTER_EN_16BIT_A;
architecture SCHEMATIC of COUNTER_EN_16BIT_A is
attribute syn_macro : integer;
attribute dont_touch : boolean;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute dont_touch of SCHEMATIC : architecture is TRUE;
signal enable_8bit_h : STD_LOGIC;
signal count_DUMMY : STD_LOGIC_VECTOR (15 downto 0);
component COUNTER_EN_8BIT_A_II
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0) );
end component;
component COUNTER_EN_8BIT_A_I
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
en_8bit_a : Out STD_LOGIC );
end component;
begin
count(15 downto 0) <= count_DUMMY(15 downto 0);
I6 : COUNTER_EN_8BIT_A_II
Port Map ( clear=>clear, clk=>clk, enable=>enable_8bit_h,
count(7 downto 0)=>count_DUMMY(15 downto 8) );
I7 : COUNTER_EN_8BIT_A_I
Port Map ( clear=>clear, clk=>clk, enable=>enable,
count(7 downto 0)=>count_DUMMY(7 downto 0),
en_8bit_a=>enable_8bit_h );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity example_en_16bit_a is
Port ( clear_in : In STD_LOGIC;
clk_in : In STD_LOGIC;
enable_in : In STD_LOGIC;
count_out : Out STD_LOGIC_VECTOR (15 downto 0) );
attribute syn_isclock: boolean;
attribute syn_isclock of clk_in: signal is true;
end example_en_16bit_a;
architecture SCHEMATIC of example_en_16bit_a is
attribute syn_macro : integer;
attribute dont_touch : boolean;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute dont_touch of SCHEMATIC : architecture is TRUE;
signal count_reg : STD_LOGIC_VECTOR (15 downto 0);
signal count : STD_LOGIC_VECTOR (15 downto 0);
signal enable_reg : STD_LOGIC;
signal enable : STD_LOGIC;
signal clear : STD_LOGIC;
signal clk : STD_LOGIC;
signal count_out_DUMMY : STD_LOGIC_VECTOR (15 downto 0);
component COUNTER_EN_16BIT_A
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (15 downto 0) );
end component;
component OPAD16_25UM
Port ( A : In STD_LOGIC_VECTOR (15 downto 0);
P : Out STD_LOGIC_VECTOR (15 downto 0) );
end component;
component INPAD_25UM
Port ( P : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component CKPAD_25UM
Port ( P : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component RG16_25UM
Port ( CLK : In STD_LOGIC;
D : In STD_LOGIC_VECTOR (15 downto 0);
Q : Out STD_LOGIC_VECTOR (15 downto 0) );
end component;
component DFF_2
Port ( CLK : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
Q1 : Out STD_LOGIC;
Q2 : Out STD_LOGIC );
end component;
begin
count_out(15 downto 0) <= count_out_DUMMY(15 downto 0);
I9 : COUNTER_EN_16BIT_A
Port Map ( clear=>clear, clk=>clk, enable=>enable_reg,
count(15 downto 0)=>count(15 downto 0) );
I1 : OPAD16_25UM
Port Map ( A(15 downto 0)=>count_reg(15 downto 0),
P(15 downto 0)=>count_out_DUMMY(15 downto 0) );
I2 : INPAD_25UM
Port Map ( P=>enable_in, Q=>enable );
I3 : CKPAD_25UM
Port Map ( P=>clear_in, Q=>clear );
I4 : CKPAD_25UM
Port Map ( P=>clk_in, Q=>clk );
I5 : RG16_25UM
Port Map ( CLK=>clk, D(15 downto 0)=>count(15 downto 0),
Q(15 downto 0)=>count_reg(15 downto 0) );
I6 : DFF_2
Port Map ( CLK=>clk, D1=>enable, D2=>enable, Q1=>enable_reg,
Q2=>open );
end SCHEMATIC;
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