?? example_en_24bit_a.vhh
字號(hào):
entity example_en_24bit_a is
Port ( clear_in : In STD_LOGIC;
clk_in : In STD_LOGIC;
enable_in : In STD_LOGIC;
count_val : Out STD_LOGIC_VECTOR (23 downto 0) );
attribute syn_isclock: boolean;
attribute syn_isclock of clk_in: signal is true;
end example_en_24bit_a;
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