?? example_en_24bit_a.v
字號:
/* Verilog Model Created from SCS Schematic example_en_24bit_a.sch
Aug 18, 2004 17:55 */
/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
`ifdef synthesis
`else
`define synthesis
`endif
`endif
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR 2
`define INCELL 3
`define CLOCK 4
`define HSCK 5
`define CLOCKB 6
`define ESPXCLKIN 7
`define HSCKMUX 8
`define IOCONTROL 9
module example_en_24bit_a( clear_in , clk_in, enable_in, count_val );
input clear_in;
input clk_in /* synthesis syn_isclock=1 */;
//exemplar attribute clk_in syn_isclock true
output [23:0] count_val;
input enable_in;
// exemplar attribute example_en_24bit_a dont_touch true
parameter syn_macro = 1;
wire [23:0] count_out;
wire [23:0] count;
wire enable_reg;
wire enable;
wire clear;
wire clk;
counter_en_24bit_a I9 ( .clear(clear), .clk(clk), .count({ count[23:0] }),
.enable(enable_reg) );
outpad_25um \outpad_25um[23] ( .A(count_out[23]), .P(count_val[23]) );
outpad_25um \outpad_25um[22] ( .A(count_out[22]), .P(count_val[22]) );
outpad_25um \outpad_25um[21] ( .A(count_out[21]), .P(count_val[21]) );
outpad_25um \outpad_25um[20] ( .A(count_out[20]), .P(count_val[20]) );
outpad_25um \outpad_25um[19] ( .A(count_out[19]), .P(count_val[19]) );
outpad_25um \outpad_25um[18] ( .A(count_out[18]), .P(count_val[18]) );
outpad_25um \outpad_25um[17] ( .A(count_out[17]), .P(count_val[17]) );
outpad_25um \outpad_25um[16] ( .A(count_out[16]), .P(count_val[16]) );
outpad_25um \outpad_25um[15] ( .A(count_out[15]), .P(count_val[15]) );
outpad_25um \outpad_25um[14] ( .A(count_out[14]), .P(count_val[14]) );
outpad_25um \outpad_25um[13] ( .A(count_out[13]), .P(count_val[13]) );
outpad_25um \outpad_25um[12] ( .A(count_out[12]), .P(count_val[12]) );
outpad_25um \outpad_25um[11] ( .A(count_out[11]), .P(count_val[11]) );
outpad_25um \outpad_25um[10] ( .A(count_out[10]), .P(count_val[10]) );
outpad_25um \outpad_25um[9] ( .A(count_out[9]), .P(count_val[9]) );
outpad_25um \outpad_25um[8] ( .A(count_out[8]), .P(count_val[8]) );
outpad_25um \outpad_25um[7] ( .A(count_out[7]), .P(count_val[7]) );
outpad_25um \outpad_25um[6] ( .A(count_out[6]), .P(count_val[6]) );
outpad_25um \outpad_25um[5] ( .A(count_out[5]), .P(count_val[5]) );
outpad_25um \outpad_25um[4] ( .A(count_out[4]), .P(count_val[4]) );
outpad_25um \outpad_25um[3] ( .A(count_out[3]), .P(count_val[3]) );
outpad_25um \outpad_25um[2] ( .A(count_out[2]), .P(count_val[2]) );
outpad_25um \outpad_25um[1] ( .A(count_out[1]), .P(count_val[1]) );
outpad_25um \outpad_25um[0] ( .A(count_out[0]), .P(count_val[0]) );
inpad_25um I1 ( .P(enable_in), .Q(enable) );
ckpad_25um I2 ( .P(clear_in), .Q(clear) );
ckpad_25um I3 ( .P(clk_in), .Q(clk) );
rg8_25um I4 ( .CLK(clk), .D({ count[7:0] }), .Q({ count_out[7:0] }) );
rg16_25um I5 ( .CLK(clk), .D({ count[23:8] }), .Q({ count_out[23:8] }) );
dff_2 I6 ( .CLK(clk), .D1(enable), .D2(enable), .Q1(enable_reg) );
endmodule // example_en_24bit_a
`ifdef counter_en_24bit_a
`else
`define counter_en_24bit_a
module counter_en_24bit_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
output [23:0] count;
input enable;
// exemplar attribute counter_en_24bit_a dont_touch true
parameter syn_macro = 1;
wire enable_24bit1_a;
wire enable24bit_h_a;
supply0 gnd;
counter_en_8bit_ii_a I15 ( .clear(clear), .clk(clk), .count({ count[23:16] }),
.enable(enable24bit_h_a) );
counter_en_16bit_a I16 ( .clear(clear), .clk(clk), .count({ count[15:0] }),
.enable(enable) );
super_logic I1 ( .A1(count[6]), .A2(gnd), .A3(count[5]), .A4(gnd), .A5(count[4]),
.A6(gnd), .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd), .D1(gnd),
.D2(gnd), .E1(count[2]), .E2(gnd), .F1(count[0]), .F2(gnd),
.F3(enable_24bit1_a), .F4(gnd), .F5(enable), .F6(gnd), .MP(gnd),
.MS(gnd), .NP(count[1]), .NS(gnd), .OP(count[3]), .OS(gnd),
.OZ(enable24bit_h_a), .PP(gnd), .PS(gnd), .QC(gnd), .QR(gnd),
.QS(gnd), .AZ(), .FZ(), .NZ(), .Q2Z(), .QZ() );
super_logic I2 ( .A1(count[15]), .A2(gnd), .A3(count[14]), .A4(gnd),
.A5(count[13]), .A6(gnd), .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd),
.D1(gnd), .D2(gnd), .E1(count[11]), .E2(gnd), .F1(count[9]),
.F2(gnd), .F3(count[8]), .F4(gnd), .F5(count[7]), .F6(gnd),
.MP(gnd), .MS(gnd), .NP(count[10]), .NS(gnd), .OP(count[12]),
.OS(gnd), .OZ(enable_24bit1_a), .PP(gnd), .PS(gnd), .QC(gnd),
.QR(gnd), .QS(gnd), .AZ(), .FZ(), .NZ(), .Q2Z(), .QZ() );
endmodule // counter_en_24bit_a
`endif
`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
// exemplar attribute outpad_25um dont_touch true
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;
eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
.IQR(GND), .OQI(A), .OSEL(VCC) );
endmodule // outpad_25um
`endif
`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
// exemplar attribute inpad_25um dont_touch true
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;
eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
.IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );
endmodule // inpad_25um
`endif
`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P /* synthesis syn_isclock=1 */;
//exemplar attribute P syn_isclock true
output Q;
// exemplar attribute ckpad_25um dont_touch true
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;
ckcell_25um I1 ( .IC(Q), .IP(P) );
endmodule // ckpad_25um
`endif
`ifdef rg8_25um
`else
`define rg8_25um
module rg8_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
input [7:0] D;
output [7:0] Q;
// exemplar attribute rg8_25um dont_touch true
parameter syn_macro = 1;
dff_2 I3 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I4 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
dff_2 I6 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
endmodule // rg8_25um
`endif
`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
input [15:0] D;
output [15:0] Q;
// exemplar attribute rg16_25um dont_touch true
parameter syn_macro = 1;
dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );
endmodule // rg16_25um
`endif
`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
input D1, D2;
output Q1, Q2;
// exemplar attribute dff_2 dont_touch true
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;
super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
.B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
.E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
.F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
.OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
.QR(gnd), .QS(gnd), .QZ(Q1), .AZ(), .FZ(), .NZ(), .OZ() );
endmodule // dff_2
`endif
`ifdef counter_en_8bit_ii_a
`else
`define counter_en_8bit_ii_a
module counter_en_8bit_ii_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
output [7:0] count;
input enable;
// exemplar attribute counter_en_8bit_ii_a dont_touch true
parameter syn_macro = 1;
wire enable_8bit;
counter_en_4bit_s I4 ( .clear(clear), .clk(clk), .enable(enable_8bit),
.qa_r(count[7]), .qb_r(count[6]), .qc_r(count[5]),
.qd_r(count[4]) );
counter_en_4bit_a I5 ( .clear(clear), .clk(clk), .enable(enable),
.enablehbit_a(enable_8bit), .qa_r(count[3]),
.qb_r(count[2]), .qc_r(count[1]), .qd_r(count[0]) );
endmodule // counter_en_8bit_ii_a
`endif
`ifdef counter_en_16bit_a
`else
`define counter_en_16bit_a
module counter_en_16bit_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
output [15:0] count;
input enable;
// exemplar attribute counter_en_16bit_a dont_touch true
parameter syn_macro = 1;
wire enable_8bit_h;
counter_en_8bit_ii_a I6 ( .clear(clear), .clk(clk), .count({ count[15:8] }),
.enable(enable_8bit_h) );
counter_en_8bit_i_a I7 ( .clear(clear), .clk(clk), .count({ count[7:0] }),
.en_8bit_a(enable_8bit_h), .enable(enable) );
endmodule // counter_en_16bit_a
`endif
`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -