?? example_8bit_load.qdf

?? VHDL examples for counter design, use QuickLogic eclips
?? QDF
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# Created by ECS2SPDE version 9.5 Release Build2
# Fri Aug 15 10:40:59 2003

QDIF 3
file ql8325
package PS484
tools
  design 9500
end
library EXAMPLE_8BIT_LOAD
  gates 4
  terms 51
  ports 58
  gate INPAD_25UM cell BIDIR
    term vcc port OSEL port OQI port ESEL port EQE end
    term gnd port IQC port IE port IQE port IQR end
    term P port IP end
    term Q port IZ end
  end
  gate CKPAD_25UM cell CLOCK
    term P port IP end
    term Q port IC end
    term VCC end
    term GND end
  end
  gate SUPER_LOGIC cell LOGIC
    term A1 port A1 end
    term A2 port A2 end
    term A3 port A3 end
    term A4 port A4 end
    term A5 port A5 end
    term A6 port A6 end
    term B1 port B1 end
    term B2 port B2 end
    term C1 port C1 end
    term C2 port C2 end
    term D1 port D1 end
    term D2 port D2 end
    term E1 port E1 end
    term E2 port E2 end
    term F1 port F1 end
    term F2 port F2 end
    term F3 port F3 end
    term F4 port F4 end
    term F5 port F5 end
    term F6 port F6 end
    term MP port MP end
    term MS port MS end
    term NP port NP end
    term NS port NS end
    term OP port OP end
    term OS port OS end
    term PP port PP end
    term PS port PS end
    term QC port QC end
    term QR port QR end
    term QS port QS end
    term AZ port AZ end
    term FZ port FZ end
    term NZ port NZ end
    term OZ port OZ end
    term Q2Z port Q2Z end
    term QZ port QZ end
    term VCC end
    term GND end
  end
  gate OUTPAD_25UM cell BIDIR
    term VCC port EQE port IE port OSEL port ESEL end
    term GND port IQC port IQE port IQR end
    term A port OQI end
    term P port IP end
  end
end
logical example_8bit_load
  gates 39
  nets 148
  gate I1.I3.I2 master SUPER_LOGIC end
  gate I1.I4.I2 master SUPER_LOGIC end
  gate I1.I5.I2 master SUPER_LOGIC end
  gate I1.I6.I2 master SUPER_LOGIC end
  gate I2.I3.I2 master SUPER_LOGIC end
  gate I2.I4.I2 master SUPER_LOGIC end
  gate I2.I5.I2 master SUPER_LOGIC end
  gate I2.I6.I2 master SUPER_LOGIC end
  gate I3.I2 master SUPER_LOGIC end
  gate I4.I1 master OUTPAD_25UM end
  gate I4.I2 master OUTPAD_25UM end
  gate I4.I3 master OUTPAD_25UM end
  gate I4.I4 master OUTPAD_25UM end
  gate I4.I5 master OUTPAD_25UM end
  gate I4.I6 master OUTPAD_25UM end
  gate I4.I7 master OUTPAD_25UM end
  gate I4.I8 master OUTPAD_25UM end
  gate I5.I1 master INPAD_25UM end
  gate I5.I2 master INPAD_25UM end
  gate I5.I3 master INPAD_25UM end
  gate I5.I4 master INPAD_25UM end
  gate I5.I5 master INPAD_25UM end
  gate I5.I6 master INPAD_25UM end
  gate I5.I7 master INPAD_25UM end
  gate I5.I8 master INPAD_25UM end
  gate I6 master INPAD_25UM end
  gate I7 master INPAD_25UM end
  gate I8 master CKPAD_25UM end
  gate I9 master CKPAD_25UM end
  gate I12.I14 master SUPER_LOGIC pack end
  gate I12.I19 master SUPER_LOGIC pack end
  gate I12.I22.I3 master SUPER_LOGIC end
  gate I12.I22.I16 master SUPER_LOGIC end
  gate I12.I22.I17 master SUPER_LOGIC end
  gate I12.I22.I18 master SUPER_LOGIC end
  gate I12.I23.I3 master SUPER_LOGIC end
  gate I12.I23.I16 master SUPER_LOGIC end
  gate I12.I23.I17 master SUPER_LOGIC end
  gate I12.I23.I18 master SUPER_LOGIC end
  net VCC
    gate I12.I23.I3 term A1 end
    gate I12.I23.I3 term A3 end
    gate I12.I23.I3 term A5 end
    gate I12.I23.I3 term OP end
    gate I12.I23.I3 term E1 end
    gate I12.I23.I3 term F1 end
    gate I12.I23.I3 term F3 end
    gate I12.I23.I3 term F5 end
    gate I12.I23.I3 term PP end
    gate I12.I23.I18 term A3 end
    gate I12.I23.I18 term A5 end
    gate I12.I23.I18 term E1 end
    gate I12.I23.I18 term F3 end
    gate I12.I23.I18 term F5 end
    gate I12.I23.I18 term PP end
    gate I12.I23.I16 term A1 end
    gate I12.I23.I16 term A3 end
    gate I12.I23.I16 term A5 end
    gate I12.I23.I16 term E1 end
    gate I12.I23.I16 term PP end
    gate I12.I23.I17 term A1 end
    gate I12.I23.I17 term A3 end
    gate I12.I23.I17 term A5 end
    gate I12.I23.I17 term E1 end
    gate I12.I23.I17 term F5 end
    gate I12.I23.I17 term PP end
    gate I12.I22.I3 term A1 end
    gate I12.I22.I3 term A3 end
    gate I12.I22.I3 term A5 end
    gate I12.I22.I3 term OP end
    gate I12.I22.I3 term E1 end
    gate I12.I22.I3 term F1 end
    gate I12.I22.I3 term F3 end
    gate I12.I22.I3 term F5 end
    gate I12.I22.I3 term PP end
    gate I12.I22.I18 term A3 end
    gate I12.I22.I18 term A5 end
    gate I12.I22.I18 term E1 end
    gate I12.I22.I18 term F3 end
    gate I12.I22.I18 term F5 end
    gate I12.I22.I18 term PP end
    gate I12.I22.I16 term A1 end
    gate I12.I22.I16 term A3 end
    gate I12.I22.I16 term A5 end
    gate I12.I22.I16 term E1 end
    gate I12.I22.I16 term PP end
    gate I12.I22.I17 term A1 end
    gate I12.I22.I17 term A3 end
    gate I12.I22.I17 term A5 end
    gate I12.I22.I17 term E1 end
    gate I12.I22.I17 term F5 end
    gate I12.I22.I17 term PP end
    gate I12.I19 term F3 end
    gate I12.I19 term OP end
    gate I12.I19 term F5 end
    gate I12.I14 term OP end
    gate I12.I14 term E1 end
    gate I12.I14 term F5 end
    gate I3.I2 term PP end
    gate I3.I2 term F5 end
    gate I3.I2 term F3 end
    gate I3.I2 term F1 end
    gate I3.I2 term NS end
    gate I3.I2 term D1 end
    gate I3.I2 term C1 end
    gate I3.I2 term B1 end
    gate I3.I2 term MS end
    gate I3.I2 term OS end
    gate I3.I2 term A5 end
    gate I3.I2 term A3 end
    gate I3.I2 term A1 end
    gate I2.I6.I2 term PP end
    gate I2.I6.I2 term F5 end
    gate I2.I6.I2 term F3 end
    gate I2.I6.I2 term F1 end
    gate I2.I6.I2 term NS end
    gate I2.I6.I2 term D1 end
    gate I2.I6.I2 term C1 end
    gate I2.I6.I2 term B1 end
    gate I2.I6.I2 term MS end
    gate I2.I6.I2 term OS end
    gate I2.I6.I2 term A5 end
    gate I2.I6.I2 term A3 end
    gate I2.I6.I2 term A1 end
    gate I2.I5.I2 term PP end
    gate I2.I5.I2 term F5 end
    gate I2.I5.I2 term F3 end
    gate I2.I5.I2 term F1 end
    gate I2.I5.I2 term NS end
    gate I2.I5.I2 term D1 end
    gate I2.I5.I2 term C1 end
    gate I2.I5.I2 term B1 end
    gate I2.I5.I2 term MS end
    gate I2.I5.I2 term OS end
    gate I2.I5.I2 term A5 end
    gate I2.I5.I2 term A3 end
    gate I2.I5.I2 term A1 end
    gate I2.I4.I2 term PP end
    gate I2.I4.I2 term F5 end
    gate I2.I4.I2 term F3 end
    gate I2.I4.I2 term F1 end
    gate I2.I4.I2 term NS end
    gate I2.I4.I2 term D1 end
    gate I2.I4.I2 term C1 end
    gate I2.I4.I2 term B1 end
    gate I2.I4.I2 term MS end
    gate I2.I4.I2 term OS end
    gate I2.I4.I2 term A5 end
    gate I2.I4.I2 term A3 end
    gate I2.I4.I2 term A1 end
    gate I2.I3.I2 term PP end
    gate I2.I3.I2 term F5 end
    gate I2.I3.I2 term F3 end
    gate I2.I3.I2 term F1 end
    gate I2.I3.I2 term NS end
    gate I2.I3.I2 term D1 end
    gate I2.I3.I2 term C1 end
    gate I2.I3.I2 term B1 end
    gate I2.I3.I2 term MS end
    gate I2.I3.I2 term OS end
    gate I2.I3.I2 term A5 end
    gate I2.I3.I2 term A3 end
    gate I2.I3.I2 term A1 end
    gate I1.I6.I2 term PP end
    gate I1.I6.I2 term F5 end
    gate I1.I6.I2 term F3 end
    gate I1.I6.I2 term F1 end
    gate I1.I6.I2 term NS end
    gate I1.I6.I2 term D1 end
    gate I1.I6.I2 term C1 end
    gate I1.I6.I2 term B1 end
    gate I1.I6.I2 term MS end
    gate I1.I6.I2 term OS end
    gate I1.I6.I2 term A5 end
    gate I1.I6.I2 term A3 end
    gate I1.I6.I2 term A1 end
    gate I1.I5.I2 term PP end
    gate I1.I5.I2 term F5 end
    gate I1.I5.I2 term F3 end
    gate I1.I5.I2 term F1 end
    gate I1.I5.I2 term NS end
    gate I1.I5.I2 term D1 end
    gate I1.I5.I2 term C1 end
    gate I1.I5.I2 term B1 end
    gate I1.I5.I2 term MS end
    gate I1.I5.I2 term OS end
    gate I1.I5.I2 term A5 end
    gate I1.I5.I2 term A3 end
    gate I1.I5.I2 term A1 end
    gate I1.I4.I2 term PP end
    gate I1.I4.I2 term F5 end
    gate I1.I4.I2 term F3 end
    gate I1.I4.I2 term F1 end
    gate I1.I4.I2 term NS end
    gate I1.I4.I2 term D1 end
    gate I1.I4.I2 term C1 end
    gate I1.I4.I2 term B1 end
    gate I1.I4.I2 term MS end
    gate I1.I4.I2 term OS end
    gate I1.I4.I2 term A5 end
    gate I1.I4.I2 term A3 end
    gate I1.I4.I2 term A1 end
    gate I1.I3.I2 term PP end
    gate I1.I3.I2 term F5 end
    gate I1.I3.I2 term F3 end
    gate I1.I3.I2 term F1 end
    gate I1.I3.I2 term NS end
    gate I1.I3.I2 term D1 end
    gate I1.I3.I2 term C1 end
    gate I1.I3.I2 term B1 end
    gate I1.I3.I2 term MS end
    gate I1.I3.I2 term OS end
    gate I1.I3.I2 term A5 end
    gate I1.I3.I2 term A3 end
    gate I1.I3.I2 term A1 end
  end
  net GND
    gate I12.I23.I18 term F6 end
    gate I12.I23.I18 term F4 end
    gate I12.I23.I18 term F2 end
    gate I12.I23.I18 term NS end
    gate I12.I23.I18 term D2 end
    gate I12.I23.I18 term C2 end
    gate I12.I23.I18 term C1 end
    gate I12.I23.I18 term B2 end
    gate I12.I23.I18 term MP end
    gate I12.I23.I18 term MS end
    gate I12.I23.I18 term OP end
    gate I12.I23.I18 term A6 end
    gate I12.I23.I18 term A4 end
    gate I12.I23.I18 term A2 end
    gate I12.I23.I18 term QS end
    gate I12.I23.I3 term F6 end
    gate I12.I23.I3 term F4 end
    gate I12.I23.I3 term F2 end
    gate I12.I23.I3 term NS end
    gate I12.I23.I3 term D2 end
    gate I12.I23.I3 term C2 end
    gate I12.I23.I3 term C1 end
    gate I12.I23.I3 term B2 end
    gate I12.I23.I3 term MP end
    gate I12.I23.I3 term MS end
    gate I12.I23.I3 term OS end
    gate I12.I23.I3 term A6 end
    gate I12.I23.I3 term A4 end
    gate I12.I23.I3 term QS end
    gate I12.I23.I16 term F6 end
    gate I12.I23.I16 term F4 end
    gate I12.I23.I16 term F2 end
    gate I12.I23.I16 term NS end
    gate I12.I23.I16 term D2 end
    gate I12.I23.I16 term C2 end
    gate I12.I23.I16 term C1 end
    gate I12.I23.I16 term B2 end
    gate I12.I23.I16 term MP end
    gate I12.I23.I16 term MS end
    gate I12.I23.I16 term OP end
    gate I12.I23.I16 term A6 end
    gate I12.I23.I16 term A4 end
    gate I12.I23.I16 term A2 end
    gate I12.I23.I16 term QS end
    gate I12.I23.I17 term F6 end
    gate I12.I23.I17 term F4 end
    gate I12.I23.I17 term F2 end
    gate I12.I23.I17 term NS end
    gate I12.I23.I17 term D2 end
    gate I12.I23.I17 term C2 end
    gate I12.I23.I17 term C1 end
    gate I12.I23.I17 term B2 end
    gate I12.I23.I17 term MP end
    gate I12.I23.I17 term MS end
    gate I12.I23.I17 term OP end
    gate I12.I23.I17 term A6 end
    gate I12.I23.I17 term A4 end
    gate I12.I23.I17 term A2 end
    gate I12.I23.I17 term QS end
    gate I12.I22.I18 term F6 end
    gate I12.I22.I18 term F4 end
    gate I12.I22.I18 term F2 end
    gate I12.I22.I18 term NS end
    gate I12.I22.I18 term D2 end
    gate I12.I22.I18 term C2 end
    gate I12.I22.I18 term C1 end
    gate I12.I22.I18 term B2 end
    gate I12.I22.I18 term MP end
    gate I12.I22.I18 term MS end
    gate I12.I22.I18 term OP end
    gate I12.I22.I18 term A6 end
    gate I12.I22.I18 term A4 end
    gate I12.I22.I18 term A2 end
    gate I12.I22.I18 term QS end
    gate I12.I22.I3 term F6 end
    gate I12.I22.I3 term F4 end
    gate I12.I22.I3 term F2 end
    gate I12.I22.I3 term NS end
    gate I12.I22.I3 term D2 end
    gate I12.I22.I3 term C2 end
    gate I12.I22.I3 term C1 end
    gate I12.I22.I3 term B2 end
    gate I12.I22.I3 term MP end
    gate I12.I22.I3 term MS end
    gate I12.I22.I3 term OS end
    gate I12.I22.I3 term A6 end
    gate I12.I22.I3 term A4 end
    gate I12.I22.I3 term QS end
    gate I12.I22.I16 term F6 end
    gate I12.I22.I16 term F4 end
    gate I12.I22.I16 term F2 end
    gate I12.I22.I16 term NS end
    gate I12.I22.I16 term D2 end
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?? 文件大小 1269 K
?? 上傳用戶 zhang8818200
?? 所屬分類 VHDL/FPGA/Verilog
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?? example_8bit_load.qdf

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