?? example_8bit_load.qdf

?? VHDL examples for counter design, use QuickLogic eclips
?? QDF
?? 第 1 頁 / 共 3 頁
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    gate I12.I22.I16 term C2 end
    gate I12.I22.I16 term C1 end
    gate I12.I22.I16 term B2 end
    gate I12.I22.I16 term MP end
    gate I12.I22.I16 term MS end
    gate I12.I22.I16 term OP end
    gate I12.I22.I16 term A6 end
    gate I12.I22.I16 term A4 end
    gate I12.I22.I16 term A2 end
    gate I12.I22.I16 term QS end
    gate I12.I22.I17 term F6 end
    gate I12.I22.I17 term F4 end
    gate I12.I22.I17 term F2 end
    gate I12.I22.I17 term NS end
    gate I12.I22.I17 term D2 end
    gate I12.I22.I17 term C2 end
    gate I12.I22.I17 term C1 end
    gate I12.I22.I17 term B2 end
    gate I12.I22.I17 term MP end
    gate I12.I22.I17 term MS end
    gate I12.I22.I17 term OP end
    gate I12.I22.I17 term A6 end
    gate I12.I22.I17 term A4 end
    gate I12.I22.I17 term A2 end
    gate I12.I22.I17 term QS end
    gate I12.I19 term D2 end
    gate I12.I19 term C2 end
    gate I12.I19 term C1 end
    gate I12.I19 term B2 end
    gate I12.I19 term B1 end
    gate I12.I19 term MP end
    gate I12.I19 term MS end
    gate I12.I19 term OS end
    gate I12.I19 term A6 end
    gate I12.I19 term A4 end
    gate I12.I19 term A2 end
    gate I12.I19 term QS end
    gate I12.I19 term E1 end
    gate I12.I19 term E2 end
    gate I12.I19 term NP end
    gate I12.I19 term NS end
    gate I12.I19 term F2 end
    gate I12.I19 term F4 end
    gate I12.I19 term F6 end
    gate I12.I19 term PS end
    gate I12.I19 term PP end
    gate I12.I14 term QS end
    gate I12.I14 term A2 end
    gate I12.I14 term A4 end
    gate I12.I14 term A6 end
    gate I12.I14 term OS end
    gate I12.I14 term MS end
    gate I12.I14 term MP end
    gate I12.I14 term B1 end
    gate I12.I14 term B2 end
    gate I12.I14 term C1 end
    gate I12.I14 term C2 end
    gate I12.I14 term D2 end
    gate I12.I14 term NP end
    gate I12.I14 term F2 end
    gate I12.I14 term F4 end
    gate I12.I14 term F6 end
    gate I12.I14 term PS end
    gate I12.I14 term PP end
    gate I3.I2 term OP end
    gate I3.I2 term A6 end
    gate I3.I2 term A4 end
    gate I3.I2 term A2 end
    gate I3.I2 term QS end
    gate I3.I2 term MP end
    gate I3.I2 term B2 end
    gate I3.I2 term C2 end
    gate I3.I2 term D2 end
    gate I3.I2 term E2 end
    gate I3.I2 term NP end
    gate I3.I2 term F2 end
    gate I3.I2 term F4 end
    gate I3.I2 term F6 end
    gate I3.I2 term QR end
    gate I2.I6.I2 term OP end
    gate I2.I6.I2 term A6 end
    gate I2.I6.I2 term A4 end
    gate I2.I6.I2 term A2 end
    gate I2.I6.I2 term QS end
    gate I2.I6.I2 term MP end
    gate I2.I6.I2 term B2 end
    gate I2.I6.I2 term C2 end
    gate I2.I6.I2 term D2 end
    gate I2.I6.I2 term E2 end
    gate I2.I6.I2 term NP end
    gate I2.I6.I2 term F2 end
    gate I2.I6.I2 term F4 end
    gate I2.I6.I2 term F6 end
    gate I2.I6.I2 term QR end
    gate I2.I5.I2 term OP end
    gate I2.I5.I2 term A6 end
    gate I2.I5.I2 term A4 end
    gate I2.I5.I2 term A2 end
    gate I2.I5.I2 term QS end
    gate I2.I5.I2 term MP end
    gate I2.I5.I2 term B2 end
    gate I2.I5.I2 term C2 end
    gate I2.I5.I2 term D2 end
    gate I2.I5.I2 term E2 end
    gate I2.I5.I2 term NP end
    gate I2.I5.I2 term F2 end
    gate I2.I5.I2 term F4 end
    gate I2.I5.I2 term F6 end
    gate I2.I5.I2 term QR end
    gate I2.I4.I2 term OP end
    gate I2.I4.I2 term A6 end
    gate I2.I4.I2 term A4 end
    gate I2.I4.I2 term A2 end
    gate I2.I4.I2 term QS end
    gate I2.I4.I2 term MP end
    gate I2.I4.I2 term B2 end
    gate I2.I4.I2 term C2 end
    gate I2.I4.I2 term D2 end
    gate I2.I4.I2 term E2 end
    gate I2.I4.I2 term NP end
    gate I2.I4.I2 term F2 end
    gate I2.I4.I2 term F4 end
    gate I2.I4.I2 term F6 end
    gate I2.I4.I2 term QR end
    gate I2.I3.I2 term OP end
    gate I2.I3.I2 term A6 end
    gate I2.I3.I2 term A4 end
    gate I2.I3.I2 term A2 end
    gate I2.I3.I2 term QS end
    gate I2.I3.I2 term MP end
    gate I2.I3.I2 term B2 end
    gate I2.I3.I2 term C2 end
    gate I2.I3.I2 term D2 end
    gate I2.I3.I2 term E2 end
    gate I2.I3.I2 term NP end
    gate I2.I3.I2 term F2 end
    gate I2.I3.I2 term F4 end
    gate I2.I3.I2 term F6 end
    gate I2.I3.I2 term QR end
    gate I1.I6.I2 term OP end
    gate I1.I6.I2 term A6 end
    gate I1.I6.I2 term A4 end
    gate I1.I6.I2 term A2 end
    gate I1.I6.I2 term QS end
    gate I1.I6.I2 term MP end
    gate I1.I6.I2 term B2 end
    gate I1.I6.I2 term C2 end
    gate I1.I6.I2 term D2 end
    gate I1.I6.I2 term E2 end
    gate I1.I6.I2 term NP end
    gate I1.I6.I2 term F2 end
    gate I1.I6.I2 term F4 end
    gate I1.I6.I2 term F6 end
    gate I1.I6.I2 term QR end
    gate I1.I5.I2 term OP end
    gate I1.I5.I2 term A6 end
    gate I1.I5.I2 term A4 end
    gate I1.I5.I2 term A2 end
    gate I1.I5.I2 term QS end
    gate I1.I5.I2 term MP end
    gate I1.I5.I2 term B2 end
    gate I1.I5.I2 term C2 end
    gate I1.I5.I2 term D2 end
    gate I1.I5.I2 term E2 end
    gate I1.I5.I2 term NP end
    gate I1.I5.I2 term F2 end
    gate I1.I5.I2 term F4 end
    gate I1.I5.I2 term F6 end
    gate I1.I5.I2 term QR end
    gate I1.I4.I2 term OP end
    gate I1.I4.I2 term A6 end
    gate I1.I4.I2 term A4 end
    gate I1.I4.I2 term A2 end
    gate I1.I4.I2 term QS end
    gate I1.I4.I2 term MP end
    gate I1.I4.I2 term B2 end
    gate I1.I4.I2 term C2 end
    gate I1.I4.I2 term D2 end
    gate I1.I4.I2 term E2 end
    gate I1.I4.I2 term NP end
    gate I1.I4.I2 term F2 end
    gate I1.I4.I2 term F4 end
    gate I1.I4.I2 term F6 end
    gate I1.I4.I2 term QR end
    gate I1.I3.I2 term OP end
    gate I1.I3.I2 term A6 end
    gate I1.I3.I2 term A4 end
    gate I1.I3.I2 term A2 end
    gate I1.I3.I2 term QS end
    gate I1.I3.I2 term MP end
    gate I1.I3.I2 term B2 end
    gate I1.I3.I2 term C2 end
    gate I1.I3.I2 term D2 end
    gate I1.I3.I2 term E2 end
    gate I1.I3.I2 term NP end
    gate I1.I3.I2 term F2 end
    gate I1.I3.I2 term F4 end
    gate I1.I3.I2 term F6 end
    gate I1.I3.I2 term QR end
  end
  net clk
    gate I9 term Q end
    gate I1.I3.I2 term QC end
    gate I1.I4.I2 term QC end
    gate I1.I6.I2 term QC end
    gate I1.I5.I2 term QC end
    gate I2.I3.I2 term QC end
    gate I2.I4.I2 term QC end
    gate I2.I6.I2 term QC end
    gate I2.I5.I2 term QC end
    gate I3.I2 term QC end
    gate I12.I22.I3 term QC end
    gate I12.I22.I18 term QC end
    gate I12.I22.I16 term QC end
    gate I12.I22.I17 term QC end
    gate I12.I23.I3 term QC end
    gate I12.I23.I18 term QC end
    gate I12.I23.I16 term QC end
    gate I12.I23.I17 term QC end
    gate I12.I19 term QC end
    gate I12.I14 term QC end
  end
  net clear
    gate I8 term Q end
    gate I12.I22.I3 term QR end
    gate I12.I22.I18 term QR end
    gate I12.I22.I16 term QR end
    gate I12.I22.I17 term QR end
    gate I12.I23.I3 term QR end
    gate I12.I23.I18 term QR end
    gate I12.I23.I16 term QR end
    gate I12.I23.I17 term QR end
    gate I12.I19 term QR end
    gate I12.I14 term QR end
  end
  net enable
    gate I7 term Q end
    gate I3.I2 term E1 end
  end
  net load
    gate I6 term Q end
    gate I3.I2 term PS end
  end
  net data_in[7]
    gate I5.I4 term Q end
    gate I2.I3.I2 term PS end
  end
  net data_in[6]
    gate I5.I3 term Q end
    gate I2.I3.I2 term E1 end
  end
  net data_in[5]
    gate I5.I2 term Q end
    gate I2.I4.I2 term PS end
  end
  net data_in[4]
    gate I5.I1 term Q end
    gate I2.I4.I2 term E1 end
  end
  net data_in[3]
    gate I5.I5 term Q end
    gate I2.I6.I2 term PS end
  end
  net data_in[2]
    gate I5.I6 term Q end
    gate I2.I6.I2 term E1 end
  end
  net data_in[1]
    gate I5.I7 term Q end
    gate I2.I5.I2 term PS end
  end
  net data_in[0]
    gate I5.I8 term Q end
    gate I2.I5.I2 term E1 end
  end
  net count_reg[7]
    gate I1.I3.I2 term Q2Z end
    gate I4.I8 term A end
  end
  net count_reg[6]
    gate I1.I3.I2 term QZ end
    gate I4.I7 term A end
  end
  net count_reg[5]
    gate I1.I4.I2 term Q2Z end
    gate I4.I6 term A end
  end
  net count_reg[4]
    gate I1.I4.I2 term QZ end
    gate I4.I5 term A end
  end
  net count_reg[3]
    gate I1.I6.I2 term Q2Z end
    gate I4.I4 term A end
  end
  net count_reg[2]
    gate I1.I6.I2 term QZ end
    gate I4.I3 term A end
  end
  net count_reg[1]
    gate I1.I5.I2 term Q2Z end
    gate I4.I2 term A end
  end
  net count_reg[0]
    gate I1.I5.I2 term QZ end
    gate I4.I1 term A end
  end
  net count[7]
    gate I1.I3.I2 term PS end
    gate I12.I19 term A1 end
    gate I12.I22.I16 term Q2Z end
  end
  net count[6]
    gate I1.I3.I2 term E1 end
    gate I12.I19 term A3 end
    gate I12.I22.I17 term Q2Z end
  end
  net count[5]
    gate I1.I4.I2 term PS end
    gate I12.I19 term A5 end
    gate I12.I22.I18 term Q2Z end
  end
  net count[4]
    gate I1.I4.I2 term E1 end
    gate I12.I19 term D1 end
    gate I12.I22.I3 term Q2Z end
    gate I12.I22.I3 term D1 end
    gate I12.I22.I3 term E2 end
    gate I12.I22.I18 term F1 end
  end
  net count[3]
    gate I1.I6.I2 term PS end
    gate I12.I14 term A1 end
    gate I12.I23.I16 term Q2Z end
  end
  net count[2]
    gate I1.I6.I2 term E1 end
    gate I12.I14 term A3 end
    gate I12.I23.I17 term Q2Z end
  end
  net count[1]
    gate I1.I5.I2 term PS end
    gate I12.I14 term A5 end
    gate I12.I23.I18 term Q2Z end
  end
  net count[0]
    gate I1.I5.I2 term E1 end
    gate I12.I14 term E2 end
    gate I12.I14 term D1 end
    gate I12.I23.I3 term Q2Z end
    gate I12.I23.I3 term D1 end
    gate I12.I23.I3 term E2 end
    gate I12.I23.I18 term F1 end
  end
  net data[7] direction input
    gate I5.I4 term P end
  end
  net data[6] direction input
    gate I5.I3 term P end
  end
  net data[5] direction input
    gate I5.I2 term P end
  end
  net data[4] direction input
    gate I5.I1 term P end
  end
  net data[3] direction input
    gate I5.I5 term P end
  end
  net data[2] direction input
    gate I5.I6 term P end
  end
  net data[1] direction input
    gate I5.I7 term P end
  end
  net data[0] direction input
    gate I5.I8 term P end
  end
  net load_reg
    gate I3.I2 term Q2Z end
    gate I12.I23.I3 term A2 end
    gate I12.I22.I3 term A2 end
  end
  net enable_reg
    gate I3.I2 term QZ end
    gate I12.I19 term F1 end
?? 文件大小 1269 K
?? 上傳用戶 zhang8818200
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關(guān)標(biāo)簽

#QuickLogic #examples #counter #design
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?? example_8bit_load.qdf

?? 快捷鍵說明
