/* Verilog Model Created from SCS Schematic example_16bit_load.sch 
   Aug 15, 2003 11:19 */

/* Automatically generated by hvveri version 9.5 Release Build2 */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_16bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in, clk_in;
 output [15:0] count_out;
 input [15:0] data;
input enable_in, load_in;
parameter syn_macro = 1;
wire [15:0] data_in;
wire [15:0] count;
wire [15:0] count_reg;
wire [15:0] data_reg;
wire load_reg;
wire enable_reg;
wire clear;
wire load;
wire enable;
wire clk;

counter_16bit_load I12 ( .clear(clear), .clk(clk), .count({ count[15:0] }),
                      .data_in({ data_reg[15:0] }), .enable(enable_reg),
                      .load(load) );
rg16_25um I1 ( .CLK(clk), .D({ data_in[15:0] }), .Q({ data_reg[15:0] }) );
rg16_25um I2 ( .CLK(clk), .D({ count[15:0] }), .Q({ count_reg[15:0] }) );
dff_2 I3 ( .CLK(clk), .D1(enable), .D2(load), .Q1(enable_reg), .Q2(load_reg) );
opad16_25um I4 ( .A({ count_reg[15:0] }), .P({ count_out[15:0] }) );
ipad16_25um I5 ( .P({ data[15:0] }), .Q({ data_in[15:0] }) );
inpad_25um I6 ( .P(load_in), .Q(load) );
inpad_25um I7 ( .P(enable_in), .Q(enable) );
ckpad_25um I8 ( .P(clear_in), .Q(clear) );
ckpad_25um I9 ( .P(clk_in), .Q(clk) );

endmodule // example_16bit_load


`ifdef counter_16bit_load
`else
`define counter_16bit_load
module counter_16bit_load( clear , clk, data_in, enable, load, count );
input clear, clk;
 output [15:0] count;
 input [15:0] data_in;
input enable, load;
parameter syn_macro = 1;
wire enable_1;
wire enable_2;

counter_8bit_ii_load I10 ( .clear(clear), .clk(clk), .count({ count[15:8] }),
                        .data_in({ data_in[15:8] }), .enable(enable),
                        .enable_1(enable_1), .enable_2(enable_2),
                        .load(load) );
counter_8bit_i_load I11 ( .clear(clear), .clk(clk), .count({ count[7:0] }),
                       .data_in({ data_in[7:0] }), .enable(enable),
                       .enable_2(enable_2), .fo_enable(enable_1),
                       .load(load) );

endmodule // counter_16bit_load

`endif

`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK;
 input [15:0] D;
 output [15:0] Q;
parameter syn_macro = 1;

dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg16_25um

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK, D1, D2;
output Q1, Q2;
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1) );

endmodule // dff_2

`endif

`ifdef opad16_25um
`else
`define opad16_25um
module opad16_25um( A , P );
 input [15:0] A;
 output [15:0] P;
parameter syn_macro = 1;

outpad_25um I1 ( .A(A[0]), .P(P[0]) );
outpad_25um I2 ( .A(A[1]), .P(P[1]) );
outpad_25um I3 ( .A(A[2]), .P(P[2]) );
outpad_25um I4 ( .A(A[3]), .P(P[3]) );
outpad_25um I5 ( .A(A[4]), .P(P[4]) );
outpad_25um I6 ( .A(A[5]), .P(P[5]) );
outpad_25um I7 ( .A(A[6]), .P(P[6]) );
outpad_25um I8 ( .A(A[7]), .P(P[7]) );
outpad_25um I9 ( .A(A[8]), .P(P[8]) );
outpad_25um I10 ( .A(A[9]), .P(P[9]) );
outpad_25um I11 ( .A(A[10]), .P(P[10]) );
outpad_25um I12 ( .A(A[11]), .P(P[11]) );
outpad_25um I13 ( .A(A[12]), .P(P[12]) );
outpad_25um I14 ( .A(A[13]), .P(P[13]) );
outpad_25um I15 ( .A(A[14]), .P(P[14]) );
outpad_25um I16 ( .A(A[15]), .P(P[15]) );

endmodule // opad16_25um

`endif

`ifdef ipad16_25um
`else
`define ipad16_25um
module ipad16_25um( P , Q );
 input [15:0] P;
 output [15:0] Q;
parameter syn_macro = 1;

inpad_25um I1 ( .P(P[15]), .Q(Q[15]) );
inpad_25um I2 ( .P(P[14]), .Q(Q[14]) );
inpad_25um I3 ( .P(P[13]), .Q(Q[13]) );
inpad_25um I4 ( .P(P[12]), .Q(Q[12]) );
inpad_25um I5 ( .P(P[8]), .Q(Q[8]) );
inpad_25um I6 ( .P(P[9]), .Q(Q[9]) );
inpad_25um I7 ( .P(P[10]), .Q(Q[10]) );
inpad_25um I8 ( .P(P[11]), .Q(Q[11]) );
inpad_25um I9 ( .P(P[7]), .Q(Q[7]) );
inpad_25um I10 ( .P(P[6]), .Q(Q[6]) );
inpad_25um I11 ( .P(P[5]), .Q(Q[5]) );
inpad_25um I12 ( .P(P[4]), .Q(Q[4]) );
inpad_25um I13 ( .P(P[3]), .Q(Q[3]) );
inpad_25um I14 ( .P(P[2]), .Q(Q[2]) );
inpad_25um I15 ( .P(P[1]), .Q(Q[1]) );
inpad_25um I16 ( .P(P[0]), .Q(Q[0]) );

endmodule // ipad16_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef counter_8bit_ii_load
`else
`define counter_8bit_ii_load
module counter_8bit_ii_load( clear , clk, data_in, enable, enable_1, enable_2, load,
                             count, enable_3, enable_4 );
input clear, clk;
 output [7:0] count;
 input [7:0] data_in;
input enable, enable_1, enable_2;
output enable_3, enable_4;
input load;
parameter syn_macro = 1;
wire enable_buf;
wire load_buf2;
wire load_buf1;
supply1 vcc;
supply0 gnd;
wire enable_in2;
wire enable_in1;

counter_4bit_load I19 ( .clear(clear), .clk(clk), .data_in({ data_in[3:0] }),
                     .enable(enable_in1), .load(load_buf1), .Qa_c(count[3]),
                     .Qb_c(count[2]), .Qc_c(count[1]), .Qd_c(count[0]) );
counter_4bit_load I20 ( .clear(clear), .clk(clk), .data_in({ data_in[7:4] }),
                     .enable(enable_in2), .load(load_buf2), .Qa_c(count[7]),
                     .Qb_c(count[6]), .Qc_c(count[5]), .Qd_c(count[4]) );
super_logic I18 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(load), .A6(gnd),
               .AZ(load_buf1), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd),
               .D1(enable), .D2(gnd), .E1(vcc), .E2(gnd), .F1(load), .F2(gnd),
               .F3(vcc), .F4(gnd), .F5(vcc), .F6(gnd), .FZ(load_buf2), .MP(gnd),
               .MS(gnd), .NP(gnd), .NS(gnd), .NZ(enable_buf), .OP(gnd),
               .OS(gnd), .PP(gnd), .PS(gnd), .QC(clk), .QR(clear), .QS(gnd) );
super_logic I12 ( .A1(count[7]), .A2(gnd), .A3(count[6]), .A4(gnd), .A5(count[5]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(count[4]),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(enable_buf), .F2(gnd),
               .F3(enable_in1), .F4(gnd), .F5(enable_3), .F6(gnd),
               .FZ(enable_in2), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd),
               .OP(vcc), .OS(gnd), .PP(gnd), .PS(gnd), .QC(clk), .QR(clear),
               .QS(gnd), .QZ(enable_4) );
super_logic I15 ( .A1(count[3]), .A2(gnd), .A3(count[2]), .A4(gnd), .A5(count[1]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(count[0]),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(enable_1), .F2(gnd),
               .F3(enable_2), .F4(gnd), .F5(enable_buf), .F6(gnd),
               .FZ(enable_in1), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd),
               .OP(vcc), .OS(gnd), .PP(gnd), .PS(gnd), .QC(clk), .QR(clear),
               .QS(gnd), .QZ(enable_3) );

endmodule // counter_8bit_ii_load

`endif

`ifdef counter_8bit_i_load
`else
`define counter_8bit_i_load
module counter_8bit_i_load( clear , clk, data_in, enable, load, count, enable_2,
                            fo_enable );
input clear, clk;
 output [7:0] count;
 input [7:0] data_in;
input enable;
output enable_2, fo_enable;
input load;
parameter syn_macro = 1;