entity example_16bit_load is
      Port ( clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC;
                data : In    STD_LOGIC_VECTOR (15 downto 0);
             enable_in : In    STD_LOGIC;
             load_in : In    STD_LOGIC;
             count_out : Out   STD_LOGIC_VECTOR (15 downto 0) );
end example_16bit_load;