/* Verilog Header Created from SCS Schematic example_16bit_load.sch 
   Aug 15, 2003 11:19 */


module example_16bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in, clk_in;
 output [15:0] count_out;
 input [15:0] data;
input enable_in, load_in;