?? example_32bit_load.vhd
字號:
-- VHDL Model Created from SCS Schematic example_32bit_load.sch
-- Aug 15, 2003 13:22
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_4BIT_LOAD is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
data_in : In STD_LOGIC_VECTOR (3 downto 0);
enable : In STD_LOGIC;
load : In STD_LOGIC;
Qa_c : Out STD_LOGIC;
Qb_c : Out STD_LOGIC;
Qc_c : Out STD_LOGIC;
Qd_c : Out STD_LOGIC );
end COUNTER_4BIT_LOAD;
architecture SCHEMATIC of COUNTER_4BIT_LOAD is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal Qb_r : STD_LOGIC;
signal Qa_r : STD_LOGIC;
signal Qb_a : STD_LOGIC;
signal Qa_a : STD_LOGIC;
signal Qc_a : STD_LOGIC;
signal Qc_r : STD_LOGIC;
signal enable_buf : STD_LOGIC;
signal Qd_r : STD_LOGIC;
signal Qd_a : STD_LOGIC;
signal load_N : STD_LOGIC;
constant GND : STD_LOGIC := '0';
constant VCC : STD_LOGIC := '1';
signal Qa_c_DUMMY : STD_LOGIC;
signal Qb_c_DUMMY : STD_LOGIC;
signal Qc_c_DUMMY : STD_LOGIC;
signal Qd_c_DUMMY : STD_LOGIC;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
Qa_c <= Qa_c_DUMMY;
Qb_c <= Qb_c_DUMMY;
Qc_c <= Qc_c_DUMMY;
Qd_c <= Qd_c_DUMMY;
I17 : SUPER_LOGIC
Port Map ( A1=>vcc, A2=>gnd, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
B1=>data_in(2), B2=>gnd, C1=>gnd, C2=>gnd, D1=>Qb_r,
D2=>gnd, E1=>vcc, E2=>Qb_r, F1=>Qc_r, F2=>gnd, F3=>Qd_r,
F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd,
NP=>enable_buf, \NS\=>gnd, OP=>gnd, OS=>load_N, PP=>vcc,
PS=>Qb_a, QC=>clk, QR=>clear, QS=>gnd, AZ=>open,
FZ=>open, NZ=>open, OZ=>Qb_a, Q2Z=>Qb_c_DUMMY, QZ=>Qb_r );
I16 : SUPER_LOGIC
Port Map ( A1=>vcc, A2=>gnd, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
B1=>data_in(3), B2=>gnd, C1=>gnd, C2=>gnd, D1=>Qa_r,
D2=>gnd, E1=>vcc, E2=>Qa_r, F1=>Qb_r, F2=>gnd, F3=>Qc_r,
F4=>gnd, F5=>Qd_r, F6=>gnd, MP=>gnd, MS=>gnd,
NP=>enable_buf, \NS\=>gnd, OP=>gnd, OS=>load_N, PP=>vcc,
PS=>Qa_a, QC=>clk, QR=>clear, QS=>gnd, AZ=>open,
FZ=>open, NZ=>open, OZ=>Qa_a, Q2Z=>Qa_c_DUMMY, QZ=>Qa_r );
I18 : SUPER_LOGIC
Port Map ( A1=>enable, A2=>gnd, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
B1=>data_in(1), B2=>gnd, C1=>gnd, C2=>gnd, D1=>Qc_r,
D2=>gnd, E1=>vcc, E2=>Qc_r, F1=>Qd_c_DUMMY, F2=>gnd,
F3=>vcc, F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd,
NP=>enable_buf, \NS\=>gnd, OP=>gnd, OS=>load_N, PP=>vcc,
PS=>Qc_a, QC=>clk, QR=>clear, QS=>gnd, AZ=>enable_buf,
FZ=>open, NZ=>open, OZ=>Qc_a, Q2Z=>Qc_c_DUMMY, QZ=>Qc_r );
I3 : SUPER_LOGIC
Port Map ( A1=>vcc, A2=>load, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
B1=>data_in(0), B2=>gnd, C1=>gnd, C2=>gnd,
D1=>Qd_c_DUMMY, D2=>gnd, E1=>vcc, E2=>Qd_c_DUMMY,
F1=>vcc, F2=>gnd, F3=>vcc, F4=>gnd, F5=>vcc, F6=>gnd,
MP=>gnd, MS=>gnd, NP=>enable_buf, \NS\=>gnd, OP=>vcc,
OS=>gnd, PP=>vcc, PS=>Qd_a, QC=>clk, QR=>clear, QS=>gnd,
AZ=>load_N, FZ=>open, NZ=>open, OZ=>Qd_a,
Q2Z=>Qd_c_DUMMY, QZ=>Qd_r );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_8BIT_IV_LOAD is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
data_in : In STD_LOGIC_VECTOR (7 downto 0);
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
enable_3 : In STD_LOGIC;
enable_4 : In STD_LOGIC;
enable_5 : In STD_LOGIC;
enable_6 : In STD_LOGIC;
load : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0) );
end COUNTER_8BIT_IV_LOAD;
architecture SCHEMATIC of COUNTER_8BIT_IV_LOAD is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal enable_in1_a : STD_LOGIC;
signal enable_in2_a : STD_LOGIC;
signal enable_7_r : STD_LOGIC;
constant VCC : STD_LOGIC := '1';
constant GND : STD_LOGIC := '0';
signal count_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
component COUNTER_4BIT_LOAD
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
data_in : In STD_LOGIC_VECTOR (3 downto 0);
enable : In STD_LOGIC;
load : In STD_LOGIC;
Qa_c : Out STD_LOGIC;
Qb_c : Out STD_LOGIC;
Qc_c : Out STD_LOGIC;
Qd_c : Out STD_LOGIC );
end component;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
count(7 downto 0) <= count_DUMMY(7 downto 0);
I18 : COUNTER_4BIT_LOAD
Port Map ( clear=>clear, clk=>clk,
data_in(3 downto 0)=>data_in(3 downto 0),
enable=>enable_in1_a, load=>load, Qa_c=>count_DUMMY(3),
Qb_c=>count_DUMMY(2), Qc_c=>count_DUMMY(1),
Qd_c=>count_DUMMY(0) );
I19 : COUNTER_4BIT_LOAD
Port Map ( clear=>clear, clk=>clk,
data_in(3 downto 0)=>data_in(7 downto 4),
enable=>enable_in2_a, load=>load, Qa_c=>count_DUMMY(7),
Qb_c=>count_DUMMY(6), Qc_c=>count_DUMMY(5),
Qd_c=>count_DUMMY(4) );
I16 : SUPER_LOGIC
Port Map ( A1=>enable, A2=>gnd, A3=>enable_1, A4=>gnd,
A5=>enable_2, A6=>gnd, B1=>gnd, B2=>gnd, C1=>gnd,
C2=>gnd, D1=>gnd, D2=>gnd, E1=>vcc, E2=>gnd,
F1=>enable_4, F2=>gnd, F3=>enable_5, F4=>gnd,
F5=>enable_6, F6=>gnd, MP=>gnd, MS=>gnd, NP=>vcc,
\NS\=>gnd, OP=>enable_3, OS=>gnd, PP=>gnd, PS=>gnd,
QC=>clk, QR=>clear, QS=>gnd, AZ=>open, FZ=>open,
NZ=>open, OZ=>enable_in1_a, Q2Z=>open, QZ=>open );
I15 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(2),
A4=>gnd, A5=>count_DUMMY(1), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(0), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>enable_in1_a, F2=>gnd, F3=>enable_7_r,
F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd,
\NS\=>gnd, OP=>vcc, OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk,
QR=>clear, QS=>gnd, AZ=>open, FZ=>enable_in2_a,
NZ=>open, OZ=>open, Q2Z=>open, QZ=>enable_7_r );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_8BIT_II_LOAD is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
data_in : In STD_LOGIC_VECTOR (7 downto 0);
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
load : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
enable_3 : Out STD_LOGIC;
enable_4 : Out STD_LOGIC );
end COUNTER_8BIT_II_LOAD;
architecture SCHEMATIC of COUNTER_8BIT_II_LOAD is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal enable_buf : STD_LOGIC;
signal load_buf2 : STD_LOGIC;
signal load_buf1 : STD_LOGIC;
constant VCC : STD_LOGIC := '1';
constant GND : STD_LOGIC := '0';
signal enable_in2 : STD_LOGIC;
signal enable_in1 : STD_LOGIC;
signal count_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
signal enable_3_DUMMY : STD_LOGIC;
signal enable_4_DUMMY : STD_LOGIC;
component COUNTER_4BIT_LOAD
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
data_in : In STD_LOGIC_VECTOR (3 downto 0);
enable : In STD_LOGIC;
load : In STD_LOGIC;
Qa_c : Out STD_LOGIC;
Qb_c : Out STD_LOGIC;
Qc_c : Out STD_LOGIC;
Qd_c : Out STD_LOGIC );
end component;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
count(7 downto 0) <= count_DUMMY(7 downto 0);
enable_3 <= enable_3_DUMMY;
enable_4 <= enable_4_DUMMY;
I19 : COUNTER_4BIT_LOAD
Port Map ( clear=>clear, clk=>clk,
data_in(3 downto 0)=>data_in(3 downto 0),
enable=>enable_in1, load=>load_buf1,
Qa_c=>count_DUMMY(3), Qb_c=>count_DUMMY(2),
Qc_c=>count_DUMMY(1), Qd_c=>count_DUMMY(0) );
I20 : COUNTER_4BIT_LOAD
Port Map ( clear=>clear, clk=>clk,
data_in(3 downto 0)=>data_in(7 downto 4),
enable=>enable_in2, load=>load_buf2,
Qa_c=>count_DUMMY(7), Qb_c=>count_DUMMY(6),
Qc_c=>count_DUMMY(5), Qd_c=>count_DUMMY(4) );
I18 : SUPER_LOGIC
Port Map ( A1=>vcc, A2=>gnd, A3=>vcc, A4=>gnd, A5=>load, A6=>gnd,
B1=>gnd, B2=>gnd, C1=>vcc, C2=>gnd, D1=>enable, D2=>gnd,
E1=>vcc, E2=>gnd, F1=>load, F2=>gnd, F3=>vcc, F4=>gnd,
F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd, \NS\=>gnd,
OP=>gnd, OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk, QR=>clear,
QS=>gnd, AZ=>load_buf1, FZ=>load_buf2, NZ=>enable_buf,
OZ=>open, Q2Z=>open, QZ=>open );
I12 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(7), A2=>gnd, A3=>count_DUMMY(6),
A4=>gnd, A5=>count_DUMMY(5), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(4), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>enable_buf, F2=>gnd, F3=>enable_in1,
F4=>gnd, F5=>enable_3_DUMMY, F6=>gnd, MP=>gnd, MS=>gnd,
NP=>gnd, \NS\=>gnd, OP=>vcc, OS=>gnd, PP=>gnd, PS=>gnd,
QC=>clk, QR=>clear, QS=>gnd, AZ=>open, FZ=>enable_in2,
NZ=>open, OZ=>open, Q2Z=>open, QZ=>enable_4_DUMMY );
I15 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(2),
A4=>gnd, A5=>count_DUMMY(1), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(0), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>enable_1, F2=>gnd, F3=>enable_2, F4=>gnd,
F5=>enable_buf, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd,
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