?? example_32bit_load.vhd

?? VHDL examples for counter design, use QuickLogic eclips
?? VHD
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   signal enable_4_DUMMY : STD_LOGIC;
   signal enable_5_DUMMY : STD_LOGIC;
   signal enable_6_DUMMY : STD_LOGIC;

   component COUNTER_16BIT_LOAD
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR  (15 downto 0);
              enable : In    STD_LOGIC;
                load : In    STD_LOGIC;
               count : Out   STD_LOGIC_VECTOR  (15 downto 0);
             enable_1 : Out   STD_LOGIC;
             enable_2 : Out   STD_LOGIC;
             enable_3 : Out   STD_LOGIC;
             enable_4 : Out   STD_LOGIC );
   end component;

   component COUNTER_8BIT_III_LOAD
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR  (7 downto 0);
              enable : In    STD_LOGIC;
             enable_1 : In    STD_LOGIC;
             enable_2 : In    STD_LOGIC;
             enable_3 : In    STD_LOGIC;
             enable_4 : In    STD_LOGIC;
                load : In    STD_LOGIC;
               count : Out   STD_LOGIC_VECTOR  (7 downto 0);
             enable_5_r : Out   STD_LOGIC;
             enable_6_r : Out   STD_LOGIC );
   end component;

begin


   count(23 downto 0) <= count_DUMMY(23 downto 0);
   enable_1 <= enable_1_DUMMY;
   enable_2 <= enable_2_DUMMY;
   enable_3 <= enable_3_DUMMY;
   enable_4 <= enable_4_DUMMY;
   enable_5 <= enable_5_DUMMY;
   enable_6 <= enable_6_DUMMY;
   I8 : COUNTER_16BIT_LOAD
      Port Map ( clear=>clear, clk=>clk,
                 data_in(15 downto 0)=>data_in(15 downto 0),
                 enable=>enable, load=>load,
                 count(15 downto 0)=>count_DUMMY(15 downto 0),
                 enable_1=>enable_1_DUMMY, enable_2=>enable_2_DUMMY,
                 enable_3=>enable_3_DUMMY, enable_4=>enable_4_DUMMY );
   I9 : COUNTER_8BIT_III_LOAD
      Port Map ( clear=>clear, clk=>clk,
                 data_in(7 downto 0)=>data_in(23 downto 16),
                 enable=>enable, enable_1=>enable_1_DUMMY,
                 enable_2=>enable_2_DUMMY, enable_3=>enable_3_DUMMY,
                 enable_4=>enable_4_DUMMY, load=>load,
                 count(7 downto 0)=>count_DUMMY(23 downto 16),
                 enable_5_r=>enable_5_DUMMY, enable_6_r=>enable_6_DUMMY );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_32BIT_LOAD is
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR (31 downto 0);
              enable : In    STD_LOGIC;
                load : In    STD_LOGIC;
               count : Out   STD_LOGIC_VECTOR (31 downto 0) );
end COUNTER_32BIT_LOAD;


architecture SCHEMATIC of COUNTER_32BIT_LOAD is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal enable_6 : STD_LOGIC;
   signal enable_5 : STD_LOGIC;
   signal enable_4 : STD_LOGIC;
   signal enable_3 : STD_LOGIC;
   signal enable_2 : STD_LOGIC;
   signal enable_1 : STD_LOGIC;
   signal count_DUMMY : STD_LOGIC_VECTOR  (31 downto 0);

   component COUNTER_8BIT_IV_LOAD
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR  (7 downto 0);
              enable : In    STD_LOGIC;
             enable_1 : In    STD_LOGIC;
             enable_2 : In    STD_LOGIC;
             enable_3 : In    STD_LOGIC;
             enable_4 : In    STD_LOGIC;
             enable_5 : In    STD_LOGIC;
             enable_6 : In    STD_LOGIC;
                load : In    STD_LOGIC;
               count : Out   STD_LOGIC_VECTOR  (7 downto 0) );
   end component;

   component COUNTER_24BIT_LOAD
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR  (23 downto 0);
              enable : In    STD_LOGIC;
                load : In    STD_LOGIC;
               count : Out   STD_LOGIC_VECTOR  (23 downto 0);
             enable_1 : Out   STD_LOGIC;
             enable_2 : Out   STD_LOGIC;
             enable_3 : Out   STD_LOGIC;
             enable_4 : Out   STD_LOGIC;
             enable_5 : Out   STD_LOGIC;
             enable_6 : Out   STD_LOGIC );
   end component;

begin


   count(31 downto 0) <= count_DUMMY(31 downto 0);
   I8 : COUNTER_8BIT_IV_LOAD
      Port Map ( clear=>clear, clk=>clk,
                 data_in(7 downto 0)=>data_in(31 downto 24),
                 enable=>enable, enable_1=>enable_1, enable_2=>enable_2,
                 enable_3=>enable_3, enable_4=>enable_4,
                 enable_5=>enable_5, enable_6=>enable_6, load=>load,
                 count(7 downto 0)=>count_DUMMY(31 downto 24) );
   I9 : COUNTER_24BIT_LOAD
      Port Map ( clear=>clear, clk=>clk,
                 data_in(23 downto 0)=>data_in(23 downto 0),
                 enable=>enable, load=>load,
                 count(23 downto 0)=>count_DUMMY(23 downto 0),
                 enable_1=>enable_1, enable_2=>enable_2,
                 enable_3=>enable_3, enable_4=>enable_4,
                 enable_5=>enable_5, enable_6=>enable_6 );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
entity example_32bit_load is
      Port ( clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC;
                data : In    STD_LOGIC_VECTOR (31 downto 0);
             enable_in : In    STD_LOGIC;
             load_in : In    STD_LOGIC;
             count_out : Out   STD_LOGIC_VECTOR (31 downto 0) );
end example_32bit_load;


architecture SCHEMATIC of example_32bit_load is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal  data_in : STD_LOGIC_VECTOR (31 downto 0);
   signal count_reg : STD_LOGIC_VECTOR (31 downto 0);
   signal data_reg : STD_LOGIC_VECTOR (31 downto 0);
   signal    count : STD_LOGIC_VECTOR (31 downto 0);
   signal load_reg : STD_LOGIC;
   signal enable_reg : STD_LOGIC;
   signal    clear : STD_LOGIC;
   signal     load : STD_LOGIC;
   signal   enable : STD_LOGIC;
   signal      clk : STD_LOGIC;
   signal count_out_DUMMY : STD_LOGIC_VECTOR  (31 downto 0);

   component COUNTER_32BIT_LOAD
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR  (31 downto 0);
              enable : In    STD_LOGIC;
                load : In    STD_LOGIC;
               count : Out   STD_LOGIC_VECTOR  (31 downto 0) );
   end component;

   component OUTPAD_25UM
      Port (       A : In    STD_LOGIC;
                   P : Out   STD_LOGIC );
   end component;

   component RG16_25UM
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (15 downto 0);
                   Q : Out   STD_LOGIC_VECTOR  (15 downto 0) );
   end component;

   component DFF_2
      Port (     CLK : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  Q1 : Out   STD_LOGIC;
                  Q2 : Out   STD_LOGIC );
   end component;

   component INPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component CKPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   count_out(31 downto 0) <= count_out_DUMMY(31 downto 0);
   I17 : COUNTER_32BIT_LOAD
      Port Map ( clear=>clear, clk=>clk,
                 data_in(31 downto 0)=>data_reg(31 downto 0),
                 enable=>enable_reg, load=>load_reg,
                 count(31 downto 0)=>count(31 downto 0) );
   outpad_25umQ31Q : OUTPAD_25UM
      Port Map ( A=>count_reg(31), P=>count_out_DUMMY(31) );
   outpad_25umQ30Q : OUTPAD_25UM
      Port Map ( A=>count_reg(30), P=>count_out_DUMMY(30) );
   outpad_25umQ29Q : OUTPAD_25UM
      Port Map ( A=>count_reg(29), P=>count_out_DUMMY(29) );
   outpad_25umQ28Q : OUTPAD_25UM
      Port Map ( A=>count_reg(28), P=>count_out_DUMMY(28) );
   outpad_25umQ27Q : OUTPAD_25UM
      Port Map ( A=>count_reg(27), P=>count_out_DUMMY(27) );
   outpad_25umQ26Q : OUTPAD_25UM
      Port Map ( A=>count_reg(26), P=>count_out_DUMMY(26) );
   outpad_25umQ25Q : OUTPAD_25UM
      Port Map ( A=>count_reg(25), P=>count_out_DUMMY(25) );
   outpad_25umQ24Q : OUTPAD_25UM
      Port Map ( A=>count_reg(24), P=>count_out_DUMMY(24) );
   outpad_25umQ23Q : OUTPAD_25UM
      Port Map ( A=>count_reg(23), P=>count_out_DUMMY(23) );
   outpad_25umQ22Q : OUTPAD_25UM
      Port Map ( A=>count_reg(22), P=>count_out_DUMMY(22) );
   outpad_25umQ21Q : OUTPAD_25UM
      Port Map ( A=>count_reg(21), P=>count_out_DUMMY(21) );
   outpad_25umQ20Q : OUTPAD_25UM
      Port Map ( A=>count_reg(20), P=>count_out_DUMMY(20) );
   outpad_25umQ19Q : OUTPAD_25UM
      Port Map ( A=>count_reg(19), P=>count_out_DUMMY(19) );
   outpad_25umQ18Q : OUTPAD_25UM
      Port Map ( A=>count_reg(18), P=>count_out_DUMMY(18) );
   outpad_25umQ17Q : OUTPAD_25UM
      Port Map ( A=>count_reg(17), P=>count_out_DUMMY(17) );
   outpad_25umQ16Q : OUTPAD_25UM
      Port Map ( A=>count_reg(16), P=>count_out_DUMMY(16) );
   outpad_25umQ15Q : OUTPAD_25UM
      Port Map ( A=>count_reg(15), P=>count_out_DUMMY(15) );
   outpad_25umQ14Q : OUTPAD_25UM
      Port Map ( A=>count_reg(14), P=>count_out_DUMMY(14) );
   outpad_25umQ13Q : OUTPAD_25UM
      Port Map ( A=>count_reg(13), P=>count_out_DUMMY(13) );
   outpad_25umQ12Q : OUTPAD_25UM
      Port Map ( A=>count_reg(12), P=>count_out_DUMMY(12) );
   outpad_25umQ11Q : OUTPAD_25UM
      Port Map ( A=>count_reg(11), P=>count_out_DUMMY(11) );
   outpad_25umQ10Q : OUTPAD_25UM
      Port Map ( A=>count_reg(10), P=>count_out_DUMMY(10) );
   outpad_25umQ9Q : OUTPAD_25UM
      Port Map ( A=>count_reg(9), P=>count_out_DUMMY(9) );
   outpad_25umQ8Q : OUTPAD_25UM
      Port Map ( A=>count_reg(8), P=>count_out_DUMMY(8) );
   outpad_25umQ7Q : OUTPAD_25UM
      Port Map ( A=>count_reg(7), P=>count_out_DUMMY(7) );
   outpad_25umQ6Q : OUTPAD_25UM
      Port Map ( A=>count_reg(6), P=>count_out_DUMMY(6) );
   outpad_25umQ5Q : OUTPAD_25UM
      Port Map ( A=>count_reg(5), P=>count_out_DUMMY(5) );
   outpad_25umQ4Q : OUTPAD_25UM
      Port Map ( A=>count_reg(4), P=>count_out_DUMMY(4) );
   outpad_25umQ3Q : OUTPAD_25UM
      Port Map ( A=>count_reg(3), P=>count_out_DUMMY(3) );
   outpad_25umQ2Q : OUTPAD_25UM
      Port Map ( A=>count_reg(2), P=>count_out_DUMMY(2) );
   outpad_25umQ1Q : OUTPAD_25UM
      Port Map ( A=>count_reg(1), P=>count_out_DUMMY(1) );
   outpad_25umQ0Q : OUTPAD_25UM
      Port Map ( A=>count_reg(0), P=>count_out_DUMMY(0) );
   I15 : RG16_25UM
      Port Map ( CLK=>clk, D(15 downto 0)=>data_in(31 downto 16),
                 Q(15 downto 0)=>data_reg(31 downto 16) );
   I16 : RG16_25UM
      Port Map ( CLK=>clk, D(15 downto 0)=>count(31 downto 16),
                 Q(15 downto 0)=>count_reg(31 downto 16) );
   I2 : RG16_25UM
      Port Map ( CLK=>clk, D(15 downto 0)=>count(15 downto 0),
                 Q(15 downto 0)=>count_reg(15 downto 0) );
   I1 : RG16_25UM
      Port Map ( CLK=>clk, D(15 downto 0)=>data_in(15 downto 0),
                 Q(15 downto 0)=>data_reg(15 downto 0) );
   I3 : DFF_2
      Port Map ( CLK=>clk, D1=>enable, D2=>load, Q1=>enable_reg,
                 Q2=>load_reg );
   inpad_25umQ31Q : INPAD_25UM
      Port Map ( P=>data(31), Q=>data_in(31) );
   inpad_25umQ30Q : INPAD_25UM
      Port Map ( P=>data(30), Q=>data_in(30) );
   inpad_25umQ29Q : INPAD_25UM
      Port Map ( P=>data(29), Q=>data_in(29) );
   inpad_25umQ28Q : INPAD_25UM
      Port Map ( P=>data(28), Q=>data_in(28) );
   inpad_25umQ27Q : INPAD_25UM
      Port Map ( P=>data(27), Q=>data_in(27) );
   inpad_25umQ26Q : INPAD_25UM
      Port Map ( P=>data(26), Q=>data_in(26) );
   inpad_25umQ25Q : INPAD_25UM
      Port Map ( P=>data(25), Q=>data_in(25) );
   inpad_25umQ24Q : INPAD_25UM
      Port Map ( P=>data(24), Q=>data_in(24) );
   inpad_25umQ23Q : INPAD_25UM
      Port Map ( P=>data(23), Q=>data_in(23) );
   inpad_25umQ22Q : INPAD_25UM
      Port Map ( P=>data(22), Q=>data_in(22) );
   inpad_25umQ21Q : INPAD_25UM
      Port Map ( P=>data(21), Q=>data_in(21) );
   inpad_25umQ20Q : INPAD_25UM
      Port Map ( P=>data(20), Q=>data_in(20) );
   inpad_25umQ19Q : INPAD_25UM
      Port Map ( P=>data(19), Q=>data_in(19) );
   inpad_25umQ18Q : INPAD_25UM
      Port Map ( P=>data(18), Q=>data_in(18) );
   inpad_25umQ17Q : INPAD_25UM
      Port Map ( P=>data(17), Q=>data_in(17) );
   inpad_25umQ16Q : INPAD_25UM
      Port Map ( P=>data(16), Q=>data_in(16) );
   inpad_25umQ15Q : INPAD_25UM
      Port Map ( P=>data(15), Q=>data_in(15) );
   inpad_25umQ14Q : INPAD_25UM
      Port Map ( P=>data(14), Q=>data_in(14) );
   inpad_25umQ13Q : INPAD_25UM
      Port Map ( P=>data(13), Q=>data_in(13) );
   inpad_25umQ12Q : INPAD_25UM
      Port Map ( P=>data(12), Q=>data_in(12) );
   inpad_25umQ11Q : INPAD_25UM
      Port Map ( P=>data(11), Q=>data_in(11) );
   inpad_25umQ10Q : INPAD_25UM
      Port Map ( P=>data(10), Q=>data_in(10) );
   inpad_25umQ9Q : INPAD_25UM
      Port Map ( P=>data(9), Q=>data_in(9) );
   inpad_25umQ8Q : INPAD_25UM
      Port Map ( P=>data(8), Q=>data_in(8) );
   inpad_25umQ7Q : INPAD_25UM
      Port Map ( P=>data(7), Q=>data_in(7) );
   inpad_25umQ6Q : INPAD_25UM
      Port Map ( P=>data(6), Q=>data_in(6) );
   inpad_25umQ5Q : INPAD_25UM
      Port Map ( P=>data(5), Q=>data_in(5) );
   inpad_25umQ4Q : INPAD_25UM
      Port Map ( P=>data(4), Q=>data_in(4) );
   inpad_25umQ3Q : INPAD_25UM
      Port Map ( P=>data(3), Q=>data_in(3) );
   inpad_25umQ2Q : INPAD_25UM
      Port Map ( P=>data(2), Q=>data_in(2) );
   inpad_25umQ1Q : INPAD_25UM
      Port Map ( P=>data(1), Q=>data_in(1) );
   inpad_25umQ0Q : INPAD_25UM
      Port Map ( P=>data(0), Q=>data_in(0) );
   I6 : INPAD_25UM
      Port Map ( P=>load_in, Q=>load );
   I7 : INPAD_25UM
      Port Map ( P=>enable_in, Q=>enable );
   I8 : CKPAD_25UM
      Port Map ( P=>clear_in, Q=>clear );
   I9 : CKPAD_25UM
      Port Map ( P=>clk_in, Q=>clk );

end SCHEMATIC;
上一頁 1 23
?? 文件大小 1269 K
?? 上傳用戶 zhang8818200
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關(guān)標簽

#QuickLogic #examples #counter #design
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?? example_32bit_load.vhd

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