++++++++++++++++++++++
| Design Information |
++++++++++++++++++++++
Design:            example_4bit_load
SpDE Version:      SpDE 9.5 Release Build2
Report Generated:  Fri Aug 15 10:34:39 2003
CHIP Last Updated: N/A
Part Type:         ql8325
Speed Grade:       8
Operating Range:   Commercial
Package Type:      484 PIN PBGA
Link Check Sum: Undetermined: sequencer has not yet been run

+++++++++++++++++++++++++++
| Utilization Information |
+++++++++++++++++++++++++++
Utilized cells (preplacement):                   9 of    1536  (0.6%)
Utilized cells (postplacement):                  9 of    1536  (0.6%)
Utilized Logic cell Frags (preplacement):       42 of    9216  (0.5%)
Utilized Logic cell Frags (postplacement):      42 of    9216  (0.5%)
Utilized Fragment A :                            2
Utilized Fragment F :                            4
Utilized Fragment O :                            9
Utilized Fragment N :                            9
IO control cells:                                0 of      16  (0.0%)
Clock only cells:                                2 of       9  (22.2%)
Bi directional cells:                           10 of     310  (3.2%)
RAM cells:                                       0 of      24  (0.0%)
ECU cells:                                       0 of      12  (0.0%)
PLL cells:                                       0 of       4  (0.0%)
Flip-Flop of IO cells:                           0 of     316  (0.0%)
1st Flip-Flop of Logic cells:                    9 of    1536  (0.6%)
2nd Flip-Flop of Logic cells:                    9 of    1536  (0.6%)
Routing resources:                             170 of  119527  (0.1%)
ViaLink resources:                             126 of 3213992  (0.0%)



+++++++++++++++++++++++++++++++++++++++++++
| Clock Network Utilization by clock pads |
+++++++++++++++++++++++++++++++++++++++++++
	Clock Network                  Net                                  Pin      Quad                  Load    
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	PLLMUX_TL4                     clear                                L3       Top Left               4       
	PLLMUX_TL2                     clk                                  L1       Top Left               9       


+++++++++++++++++++++++++++++++++++++++++++++++
| Clock Network Utilization by Internal Logic |
+++++++++++++++++++++++++++++++++++++++++++++++


++++++++++++++++++++++++++++++++++++
| Clock Network Utilization by PLL |
++++++++++++++++++++++++++++++++++++

|Available HSCK Clock Networks|
	Quad TOP LEFT     : 	5 of 5 QuadNets available	(100.0%)
	Quad TOP RIGHT    : 	5 of 5 QuadNets available	(100.0%)
	Quad BOTTOM LEFT  : 	5 of 5 QuadNets available	(100.0%)
	Quad BOTTOM RIGHT : 	5 of 5 QuadNets available	(100.0%)




++++++++++++++++++
| Timing Results |
++++++++++++++++++

Summary:

Clock                               Frequency       Setup Time      Clock to Out   
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
clk_in                          410 MHz /  2.4 ns      0.8 ns          3.7 ns


Inter Clock Domain Delay Matrix
+++++++++++++++++++++++++++++++

Clock0 = clk_in 

 
          Clock0  
Clock0    2.4 ns

+++++++++++++++++++++++++++++++++++++++++
| Tools run on design example_4bit_load |
+++++++++++++++++++++++++++++++++++++++++
partdef         9.4    
design          9.5    
logic optimizer 9.5     Mode = Quality Goal = Speed IgnorePack = FALSE UseNonBondedPads = TRUE Run Time 0:00:01
placer          9.5     Seed = 42 Mode = Quality Run Time 0:00:04
router          9.51    Seed = 42 Run Time 0:00:01
delay modeler   9.5     Mode = Commercial Corner = Worst SpeedGrade = 8 LowPower = FALSE Run Time 0:00:01
verifier        9.5    
auto buffer     9.5    


+++++++++++++
| Pin Table |
+++++++++++++
Display Pin Info option is FALSE.
Pin information will not be displayed.

++++++++++++++++++++
| Fixed Flip Flops |
++++++++++++++++++++
None


+++++++++++++++++++
| Fixed RAM cells |
+++++++++++++++++++
None


+++++++++++++++++++
| Fixed ECU cells |
+++++++++++++++++++
None


+++++++++++++++++++++++++++++++++++++
| Nets Removed by Technology Mapper |
+++++++++++++++++++++++++++++++++++++
Removed Nets option is FALSE.
Removed Nets information will not be displayed.



++++++++++  The end of report file  ++++++++++