-- VHDL Model Created from SCS Schematic example_4bit_load.sch 
-- Aug 15, 2003 10:23 

-- Automatically generated by vdvhdl version 9.5 Release Build2 

library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_4BIT_LOAD is
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR (3 downto 0);
              enable : In    STD_LOGIC;
                load : In    STD_LOGIC;
                Qa_c : Out   STD_LOGIC;
                Qb_c : Out   STD_LOGIC;
                Qc_c : Out   STD_LOGIC;
                Qd_c : Out   STD_LOGIC );
end COUNTER_4BIT_LOAD;


architecture SCHEMATIC of COUNTER_4BIT_LOAD is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal     Qb_r : STD_LOGIC;
   signal     Qa_r : STD_LOGIC;
   signal     Qb_a : STD_LOGIC;
   signal     Qa_a : STD_LOGIC;
   signal     Qc_a : STD_LOGIC;
   signal     Qc_r : STD_LOGIC;
   signal enable_buf : STD_LOGIC;
   signal     Qd_r : STD_LOGIC;
   signal     Qd_a : STD_LOGIC;
   signal   load_N : STD_LOGIC;
	constant 		GND : STD_LOGIC := '0';
	constant 		VCC : STD_LOGIC := '1';
   signal Qa_c_DUMMY : STD_LOGIC;
   signal Qb_c_DUMMY : STD_LOGIC;
   signal Qc_c_DUMMY : STD_LOGIC;
   signal Qd_c_DUMMY : STD_LOGIC;

   component SUPER_LOGIC
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                  F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  MP : In    STD_LOGIC;
                  MS : In    STD_LOGIC;
                  NP : In    STD_LOGIC;
                \NS\ : In    STD_LOGIC;
                  OP : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  PP : In    STD_LOGIC;
                  PS : In    STD_LOGIC;
                  QC : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC;
                  FZ : Out   STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC;
                 Q2Z : Out   STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

begin


   Qa_c <= Qa_c_DUMMY;
   Qb_c <= Qb_c_DUMMY;
   Qc_c <= Qc_c_DUMMY;
   Qd_c <= Qd_c_DUMMY;
   I17 : SUPER_LOGIC
      Port Map ( A1=>vcc, A2=>gnd, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
                 B1=>data_in(2), B2=>gnd, C1=>gnd, C2=>gnd, D1=>Qb_r,
                 D2=>gnd, E1=>vcc, E2=>Qb_r, F1=>Qc_r, F2=>gnd, F3=>Qd_r,
                 F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd,
                 NP=>enable_buf, \NS\=>gnd, OP=>gnd, OS=>load_N, PP=>vcc,
                 PS=>Qb_a, QC=>clk, QR=>clear, QS=>gnd, AZ=>open,
                 FZ=>open, NZ=>open, OZ=>Qb_a, Q2Z=>Qb_c_DUMMY, QZ=>Qb_r );
   I16 : SUPER_LOGIC
      Port Map ( A1=>vcc, A2=>gnd, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
                 B1=>data_in(3), B2=>gnd, C1=>gnd, C2=>gnd, D1=>Qa_r,
                 D2=>gnd, E1=>vcc, E2=>Qa_r, F1=>Qb_r, F2=>gnd, F3=>Qc_r,
                 F4=>gnd, F5=>Qd_r, F6=>gnd, MP=>gnd, MS=>gnd,
                 NP=>enable_buf, \NS\=>gnd, OP=>gnd, OS=>load_N, PP=>vcc,
                 PS=>Qa_a, QC=>clk, QR=>clear, QS=>gnd, AZ=>open,
                 FZ=>open, NZ=>open, OZ=>Qa_a, Q2Z=>Qa_c_DUMMY, QZ=>Qa_r );
   I18 : SUPER_LOGIC
      Port Map ( A1=>enable, A2=>gnd, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
                 B1=>data_in(1), B2=>gnd, C1=>gnd, C2=>gnd, D1=>Qc_r,
                 D2=>gnd, E1=>vcc, E2=>Qc_r, F1=>Qd_c_DUMMY, F2=>gnd,
                 F3=>vcc, F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd,
                 NP=>enable_buf, \NS\=>gnd, OP=>gnd, OS=>load_N, PP=>vcc,
                 PS=>Qc_a, QC=>clk, QR=>clear, QS=>gnd, AZ=>enable_buf,
                 FZ=>open, NZ=>open, OZ=>Qc_a, Q2Z=>Qc_c_DUMMY, QZ=>Qc_r );
   I3 : SUPER_LOGIC
      Port Map ( A1=>vcc, A2=>load, A3=>vcc, A4=>gnd, A5=>vcc, A6=>gnd,
                 B1=>data_in(0), B2=>gnd, C1=>gnd, C2=>gnd,
                 D1=>Qd_c_DUMMY, D2=>gnd, E1=>vcc, E2=>Qd_c_DUMMY,
                 F1=>vcc, F2=>gnd, F3=>vcc, F4=>gnd, F5=>vcc, F6=>gnd,
                 MP=>gnd, MS=>gnd, NP=>enable_buf, \NS\=>gnd, OP=>vcc,
                 OS=>gnd, PP=>vcc, PS=>Qd_a, QC=>clk, QR=>clear, QS=>gnd,
                 AZ=>load_N, FZ=>open, NZ=>open, OZ=>Qd_a,
                 Q2Z=>Qd_c_DUMMY, QZ=>Qd_r );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
entity example_4bit_load is
      Port ( clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC;
                data : In    STD_LOGIC_VECTOR (3 downto 0);
             enable_in : In    STD_LOGIC;
             load_in : In    STD_LOGIC;
             count_out : Out   STD_LOGIC_VECTOR (3 downto 0) );
end example_4bit_load;


architecture SCHEMATIC of example_4bit_load is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal  data_in : STD_LOGIC_VECTOR (3 downto 0);
   signal    count : STD_LOGIC_VECTOR (3 downto 0);
   signal data_in_reg : STD_LOGIC_VECTOR (3 downto 0);
   signal count_reg : STD_LOGIC_VECTOR (3 downto 0);
   signal load_reg : STD_LOGIC;
   signal enable_reg : STD_LOGIC;
   signal     load : STD_LOGIC;
   signal   enable : STD_LOGIC;
   signal    clear : STD_LOGIC;
   signal      clk : STD_LOGIC;
   signal count_out_DUMMY : STD_LOGIC_VECTOR  (3 downto 0);

   component COUNTER_4BIT_LOAD
      Port (   clear : In    STD_LOGIC;
                 clk : In    STD_LOGIC;
             data_in : In    STD_LOGIC_VECTOR  (3 downto 0);
              enable : In    STD_LOGIC;
                load : In    STD_LOGIC;
                Qa_c : Out   STD_LOGIC;
                Qb_c : Out   STD_LOGIC;
                Qc_c : Out   STD_LOGIC;
                Qd_c : Out   STD_LOGIC );
   end component;

   component RG4_25UM
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC_VECTOR  (3 downto 0);
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

   component DFF_2
      Port (     CLK : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  Q1 : Out   STD_LOGIC;
                  Q2 : Out   STD_LOGIC );
   end component;

   component OPAD4_25UM
      Port (       A : In    STD_LOGIC_VECTOR  (3 downto 0);
                   P : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

   component IPAD4_25UM
      Port (       P : In    STD_LOGIC_VECTOR  (3 downto 0);
                   Q : Out   STD_LOGIC_VECTOR  (3 downto 0) );
   end component;

   component INPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component CKPAD_25UM
      Port (       P : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   count_out(3 downto 0) <= count_out_DUMMY(3 downto 0);
   I12 : COUNTER_4BIT_LOAD
      Port Map ( clear=>clear, clk=>clk,
                 data_in(3 downto 0)=>data_in_reg(3 downto 0),
                 enable=>enable_reg, load=>load_reg, Qa_c=>count(3),
                 Qb_c=>count(2), Qc_c=>count(1), Qd_c=>count(0) );
   I1 : RG4_25UM
      Port Map ( CLK=>clk, D(3 downto 0)=>data_in(3 downto 0),
                 Q(3 downto 0)=>data_in_reg(3 downto 0) );
   I2 : RG4_25UM
      Port Map ( CLK=>clk, D(3 downto 0)=>count(3 downto 0),
                 Q(3 downto 0)=>count_reg(3 downto 0) );
   I3 : DFF_2
      Port Map ( CLK=>clk, D1=>enable, D2=>load, Q1=>enable_reg,
                 Q2=>load_reg );
   I4 : OPAD4_25UM
      Port Map ( A(3 downto 0)=>count_reg(3 downto 0),
                 P(3 downto 0)=>count_out_DUMMY(3 downto 0) );
   I5 : IPAD4_25UM
      Port Map ( P(3 downto 0)=>data(3 downto 0),
                 Q(3 downto 0)=>data_in(3 downto 0) );
   I6 : INPAD_25UM
      Port Map ( P=>load_in, Q=>load );
   I7 : INPAD_25UM
      Port Map ( P=>enable_in, Q=>enable );
   I8 : CKPAD_25UM
      Port Map ( P=>clear_in, Q=>clear );
   I9 : CKPAD_25UM
      Port Map ( P=>clk_in, Q=>clk );

end SCHEMATIC;