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?? example_en_32bit_s.qdf

?? VHDL examples for counter design, use QuickLogic eclips
?? QDF
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# Created by ECS2SPDE version 9.5 Release Build2
# Thu Aug 14 16:38:54 2003

QDIF 3
file ql8325
package PS484
tools
  design 9500
end
library EXAMPLE_EN_32BIT_S
  gates 4
  terms 51
  ports 58
  gate OUTPAD_25UM cell BIDIR
    term VCC port EQE port IE port OSEL port ESEL end
    term GND port IQC port IQE port IQR end
    term A port OQI end
    term P port IP end
  end
  gate INPAD_25UM cell BIDIR
    term vcc port OSEL port OQI port ESEL port EQE end
    term gnd port IQC port IE port IQE port IQR end
    term P port IP end
    term Q port IZ end
  end
  gate CKPAD_25UM cell CLOCK
    term P port IP end
    term Q port IC end
    term VCC end
    term GND end
  end
  gate SUPER_LOGIC cell LOGIC
    term A1 port A1 end
    term A2 port A2 end
    term A3 port A3 end
    term A4 port A4 end
    term A5 port A5 end
    term A6 port A6 end
    term B1 port B1 end
    term B2 port B2 end
    term C1 port C1 end
    term C2 port C2 end
    term D1 port D1 end
    term D2 port D2 end
    term E1 port E1 end
    term E2 port E2 end
    term F1 port F1 end
    term F2 port F2 end
    term F3 port F3 end
    term F4 port F4 end
    term F5 port F5 end
    term F6 port F6 end
    term MP port MP end
    term MS port MS end
    term NP port NP end
    term NS port NS end
    term OP port OP end
    term OS port OS end
    term PP port PP end
    term PS port PS end
    term QC port QC end
    term QR port QR end
    term QS port QS end
    term AZ port AZ end
    term FZ port FZ end
    term NZ port NZ end
    term OZ port OZ end
    term Q2Z port Q2Z end
    term QZ port QZ end
    term VCC end
    term GND end
  end
end
logical example_en_32bit_s
  gates 77
  nets 292
  gate I1.I2.I2 master SUPER_LOGIC end
  gate I1.I3.I2 master SUPER_LOGIC end
  gate I1.I4.I2 master SUPER_LOGIC end
  gate I1.I5.I2 master SUPER_LOGIC end
  gate I1.I6.I2 master SUPER_LOGIC end
  gate I1.I7.I2 master SUPER_LOGIC end
  gate I1.I8.I2 master SUPER_LOGIC end
  gate I1.I9.I2 master SUPER_LOGIC end
  gate I2.I2.I2 master SUPER_LOGIC end
  gate I2.I3.I2 master SUPER_LOGIC end
  gate I2.I4.I2 master SUPER_LOGIC end
  gate I2.I5.I2 master SUPER_LOGIC end
  gate I2.I6.I2 master SUPER_LOGIC end
  gate I2.I7.I2 master SUPER_LOGIC end
  gate I2.I8.I2 master SUPER_LOGIC end
  gate I2.I9.I2 master SUPER_LOGIC end
  gate I3.I2 master SUPER_LOGIC end
  gate I4 master INPAD_25UM end
  gate I5 master CKPAD_25UM end
  gate I6 master CKPAD_25UM end
  gate I9.I9.I15 master SUPER_LOGIC pack end
  gate I9.I9.I16 master SUPER_LOGIC pack end
  gate I9.I9.I17.I1 master SUPER_LOGIC end
  gate I9.I9.I17.I2 master SUPER_LOGIC end
  gate I9.I9.I18.I1 master SUPER_LOGIC end
  gate I9.I9.I18.I2 master SUPER_LOGIC end
  gate I9.I10.I12 master SUPER_LOGIC pack end
  gate I9.I10.I15 master SUPER_LOGIC pack end
  gate I9.I10.I16 master SUPER_LOGIC pack end
  gate I9.I10.I17.I1 master SUPER_LOGIC end
  gate I9.I10.I17.I2 master SUPER_LOGIC end
  gate I9.I10.I18.I1 master SUPER_LOGIC end
  gate I9.I10.I18.I2 master SUPER_LOGIC end
  gate I9.I11.I12 master SUPER_LOGIC pack end
  gate I9.I11.I15 master SUPER_LOGIC pack end
  gate I9.I11.I16.I1 master SUPER_LOGIC end
  gate I9.I11.I16.I2 master SUPER_LOGIC end
  gate I9.I11.I17.I1 master SUPER_LOGIC end
  gate I9.I11.I17.I2 master SUPER_LOGIC end
  gate I9.I12.I14 master SUPER_LOGIC pack end
  gate I9.I12.I19 master SUPER_LOGIC pack end
  gate I9.I12.I20.I1 master SUPER_LOGIC end
  gate I9.I12.I20.I2 master SUPER_LOGIC end
  gate I9.I12.I21.I1 master SUPER_LOGIC end
  gate I9.I12.I21.I2 master SUPER_LOGIC end
  gate outpad_25um[31] master OUTPAD_25UM end
  gate outpad_25um[30] master OUTPAD_25UM end
  gate outpad_25um[29] master OUTPAD_25UM end
  gate outpad_25um[28] master OUTPAD_25UM end
  gate outpad_25um[27] master OUTPAD_25UM end
  gate outpad_25um[26] master OUTPAD_25UM end
  gate outpad_25um[25] master OUTPAD_25UM end
  gate outpad_25um[24] master OUTPAD_25UM end
  gate outpad_25um[23] master OUTPAD_25UM end
  gate outpad_25um[22] master OUTPAD_25UM end
  gate outpad_25um[21] master OUTPAD_25UM end
  gate outpad_25um[20] master OUTPAD_25UM end
  gate outpad_25um[19] master OUTPAD_25UM end
  gate outpad_25um[18] master OUTPAD_25UM end
  gate outpad_25um[17] master OUTPAD_25UM end
  gate outpad_25um[16] master OUTPAD_25UM end
  gate outpad_25um[15] master OUTPAD_25UM end
  gate outpad_25um[14] master OUTPAD_25UM end
  gate outpad_25um[13] master OUTPAD_25UM end
  gate outpad_25um[12] master OUTPAD_25UM end
  gate outpad_25um[11] master OUTPAD_25UM end
  gate outpad_25um[10] master OUTPAD_25UM end
  gate outpad_25um[9] master OUTPAD_25UM end
  gate outpad_25um[8] master OUTPAD_25UM end
  gate outpad_25um[7] master OUTPAD_25UM end
  gate outpad_25um[6] master OUTPAD_25UM end
  gate outpad_25um[5] master OUTPAD_25UM end
  gate outpad_25um[4] master OUTPAD_25UM end
  gate outpad_25um[3] master OUTPAD_25UM end
  gate outpad_25um[2] master OUTPAD_25UM end
  gate outpad_25um[1] master OUTPAD_25UM end
  gate outpad_25um[0] master OUTPAD_25UM end
  net VCC
    gate I9.I12.I21.I2 term A5 end
    gate I9.I12.I21.I2 term C1 end
    gate I9.I12.I21.I1 term E1 end
    gate I9.I12.I21.I1 term F5 end
    gate I9.I12.I20.I2 term A5 end
    gate I9.I12.I20.I2 term C1 end
    gate I9.I12.I20.I1 term E1 end
    gate I9.I12.I20.I1 term F5 end
    gate I9.I12.I14 term OP end
    gate I9.I12.I14 term E1 end
    gate I9.I12.I14 term F5 end
    gate I9.I12.I19 term F3 end
    gate I9.I12.I19 term OP end
    gate I9.I12.I19 term F5 end
    gate I9.I11.I17.I2 term A5 end
    gate I9.I11.I17.I2 term C1 end
    gate I9.I11.I17.I1 term E1 end
    gate I9.I11.I17.I1 term F5 end
    gate I9.I11.I16.I2 term A5 end
    gate I9.I11.I16.I2 term C1 end
    gate I9.I11.I16.I1 term E1 end
    gate I9.I11.I16.I1 term F5 end
    gate I9.I11.I12 term E1 end
    gate I9.I11.I12 term C1 end
    gate I9.I11.I12 term OP end
    gate I9.I11.I15 term OP end
    gate I9.I11.I15 term C1 end
    gate I9.I11.I15 term E1 end
    gate I9.I10.I18.I2 term A5 end
    gate I9.I10.I18.I2 term C1 end
    gate I9.I10.I18.I1 term E1 end
    gate I9.I10.I18.I1 term F5 end
    gate I9.I10.I17.I2 term A5 end
    gate I9.I10.I17.I2 term C1 end
    gate I9.I10.I17.I1 term E1 end
    gate I9.I10.I17.I1 term F5 end
    gate I9.I10.I12 term F5 end
    gate I9.I10.I12 term F3 end
    gate I9.I10.I12 term F1 end
    gate I9.I10.I12 term E1 end
    gate I9.I10.I12 term C1 end
    gate I9.I10.I12 term OP end
    gate I9.I10.I15 term OP end
    gate I9.I10.I15 term C1 end
    gate I9.I10.I15 term E1 end
    gate I9.I10.I15 term F1 end
    gate I9.I10.I15 term F3 end
    gate I9.I10.I15 term F5 end
    gate I9.I10.I16 term C1 end
    gate I9.I10.I16 term E1 end
    gate I9.I10.I16 term F5 end
    gate I9.I9.I18.I2 term A5 end
    gate I9.I9.I18.I2 term C1 end
    gate I9.I9.I18.I1 term E1 end
    gate I9.I9.I18.I1 term F5 end
    gate I9.I9.I17.I2 term A5 end
    gate I9.I9.I17.I2 term C1 end
    gate I9.I9.I17.I1 term E1 end
    gate I9.I9.I17.I1 term F5 end
    gate I9.I9.I16 term OP end
    gate I9.I9.I16 term NP end
    gate I9.I9.I15 term OP end
    gate I9.I9.I15 term C1 end
    gate I9.I9.I15 term E1 end
    gate I9.I9.I15 term F5 end
    gate I3.I2 term PP end
    gate I3.I2 term F5 end
    gate I3.I2 term F3 end
    gate I3.I2 term F1 end
    gate I3.I2 term NS end
    gate I3.I2 term D1 end
    gate I3.I2 term C1 end
    gate I3.I2 term B1 end
    gate I3.I2 term MS end
    gate I3.I2 term OS end
    gate I3.I2 term A5 end
    gate I3.I2 term A3 end
    gate I3.I2 term A1 end
    gate I2.I9.I2 term PP end
    gate I2.I9.I2 term F5 end
    gate I2.I9.I2 term F3 end
    gate I2.I9.I2 term F1 end
    gate I2.I9.I2 term NS end
    gate I2.I9.I2 term D1 end
    gate I2.I9.I2 term C1 end
    gate I2.I9.I2 term B1 end
    gate I2.I9.I2 term MS end
    gate I2.I9.I2 term OS end
    gate I2.I9.I2 term A5 end
    gate I2.I9.I2 term A3 end
    gate I2.I9.I2 term A1 end
    gate I2.I8.I2 term PP end
    gate I2.I8.I2 term F5 end
    gate I2.I8.I2 term F3 end
    gate I2.I8.I2 term F1 end
    gate I2.I8.I2 term NS end
    gate I2.I8.I2 term D1 end
    gate I2.I8.I2 term C1 end
    gate I2.I8.I2 term B1 end
    gate I2.I8.I2 term MS end
    gate I2.I8.I2 term OS end
    gate I2.I8.I2 term A5 end
    gate I2.I8.I2 term A3 end
    gate I2.I8.I2 term A1 end
    gate I2.I7.I2 term PP end
    gate I2.I7.I2 term F5 end
    gate I2.I7.I2 term F3 end
    gate I2.I7.I2 term F1 end
    gate I2.I7.I2 term NS end
    gate I2.I7.I2 term D1 end
    gate I2.I7.I2 term C1 end
    gate I2.I7.I2 term B1 end
    gate I2.I7.I2 term MS end
    gate I2.I7.I2 term OS end
    gate I2.I7.I2 term A5 end
    gate I2.I7.I2 term A3 end
    gate I2.I7.I2 term A1 end
    gate I2.I6.I2 term PP end
    gate I2.I6.I2 term F5 end
    gate I2.I6.I2 term F3 end
    gate I2.I6.I2 term F1 end
    gate I2.I6.I2 term NS end
    gate I2.I6.I2 term D1 end
    gate I2.I6.I2 term C1 end
    gate I2.I6.I2 term B1 end
    gate I2.I6.I2 term MS end
    gate I2.I6.I2 term OS end
    gate I2.I6.I2 term A5 end
    gate I2.I6.I2 term A3 end
    gate I2.I6.I2 term A1 end
    gate I2.I5.I2 term PP end
    gate I2.I5.I2 term F5 end
    gate I2.I5.I2 term F3 end
    gate I2.I5.I2 term F1 end
    gate I2.I5.I2 term NS end
    gate I2.I5.I2 term D1 end
    gate I2.I5.I2 term C1 end
    gate I2.I5.I2 term B1 end
    gate I2.I5.I2 term MS end
    gate I2.I5.I2 term OS end
    gate I2.I5.I2 term A5 end
    gate I2.I5.I2 term A3 end
    gate I2.I5.I2 term A1 end
    gate I2.I4.I2 term PP end
    gate I2.I4.I2 term F5 end
    gate I2.I4.I2 term F3 end
    gate I2.I4.I2 term F1 end
    gate I2.I4.I2 term NS end
    gate I2.I4.I2 term D1 end
    gate I2.I4.I2 term C1 end
    gate I2.I4.I2 term B1 end
    gate I2.I4.I2 term MS end
    gate I2.I4.I2 term OS end
    gate I2.I4.I2 term A5 end
    gate I2.I4.I2 term A3 end
    gate I2.I4.I2 term A1 end
    gate I2.I3.I2 term PP end
    gate I2.I3.I2 term F5 end
    gate I2.I3.I2 term F3 end
    gate I2.I3.I2 term F1 end
    gate I2.I3.I2 term NS end
    gate I2.I3.I2 term D1 end
    gate I2.I3.I2 term C1 end
    gate I2.I3.I2 term B1 end
    gate I2.I3.I2 term MS end
    gate I2.I3.I2 term OS end
    gate I2.I3.I2 term A5 end
    gate I2.I3.I2 term A3 end
    gate I2.I3.I2 term A1 end
    gate I2.I2.I2 term PP end
    gate I2.I2.I2 term F5 end
    gate I2.I2.I2 term F3 end
    gate I2.I2.I2 term F1 end
    gate I2.I2.I2 term NS end
    gate I2.I2.I2 term D1 end
    gate I2.I2.I2 term C1 end
    gate I2.I2.I2 term B1 end
    gate I2.I2.I2 term MS end
    gate I2.I2.I2 term OS end
    gate I2.I2.I2 term A5 end
    gate I2.I2.I2 term A3 end
    gate I2.I2.I2 term A1 end
    gate I1.I9.I2 term PP end
    gate I1.I9.I2 term F5 end
    gate I1.I9.I2 term F3 end
    gate I1.I9.I2 term F1 end
    gate I1.I9.I2 term NS end
    gate I1.I9.I2 term D1 end
    gate I1.I9.I2 term C1 end
    gate I1.I9.I2 term B1 end
    gate I1.I9.I2 term MS end
    gate I1.I9.I2 term OS end
    gate I1.I9.I2 term A5 end
    gate I1.I9.I2 term A3 end
    gate I1.I9.I2 term A1 end
    gate I1.I8.I2 term PP end
    gate I1.I8.I2 term F5 end
    gate I1.I8.I2 term F3 end
    gate I1.I8.I2 term F1 end
    gate I1.I8.I2 term NS end
    gate I1.I8.I2 term D1 end
    gate I1.I8.I2 term C1 end
    gate I1.I8.I2 term B1 end
    gate I1.I8.I2 term MS end
    gate I1.I8.I2 term OS end
    gate I1.I8.I2 term A5 end
    gate I1.I8.I2 term A3 end
    gate I1.I8.I2 term A1 end
    gate I1.I7.I2 term PP end
    gate I1.I7.I2 term F5 end
    gate I1.I7.I2 term F3 end
    gate I1.I7.I2 term F1 end
    gate I1.I7.I2 term NS end
    gate I1.I7.I2 term D1 end
    gate I1.I7.I2 term C1 end
    gate I1.I7.I2 term B1 end
    gate I1.I7.I2 term MS end
    gate I1.I7.I2 term OS end
    gate I1.I7.I2 term A5 end
    gate I1.I7.I2 term A3 end
    gate I1.I7.I2 term A1 end
    gate I1.I6.I2 term PP end
    gate I1.I6.I2 term F5 end
    gate I1.I6.I2 term F3 end
    gate I1.I6.I2 term F1 end
    gate I1.I6.I2 term NS end
    gate I1.I6.I2 term D1 end
    gate I1.I6.I2 term C1 end
    gate I1.I6.I2 term B1 end
    gate I1.I6.I2 term MS end
    gate I1.I6.I2 term OS end
    gate I1.I6.I2 term A5 end
    gate I1.I6.I2 term A3 end
    gate I1.I6.I2 term A1 end
    gate I1.I5.I2 term PP end
    gate I1.I5.I2 term F5 end
    gate I1.I5.I2 term F3 end
    gate I1.I5.I2 term F1 end
    gate I1.I5.I2 term NS end
    gate I1.I5.I2 term D1 end
    gate I1.I5.I2 term C1 end
    gate I1.I5.I2 term B1 end
    gate I1.I5.I2 term MS end
    gate I1.I5.I2 term OS end
    gate I1.I5.I2 term A5 end
    gate I1.I5.I2 term A3 end
    gate I1.I5.I2 term A1 end
    gate I1.I4.I2 term PP end
    gate I1.I4.I2 term F5 end
    gate I1.I4.I2 term F3 end
    gate I1.I4.I2 term F1 end
    gate I1.I4.I2 term NS end
    gate I1.I4.I2 term D1 end
    gate I1.I4.I2 term C1 end
    gate I1.I4.I2 term B1 end
    gate I1.I4.I2 term MS end
    gate I1.I4.I2 term OS end
    gate I1.I4.I2 term A5 end
    gate I1.I4.I2 term A3 end
    gate I1.I4.I2 term A1 end
    gate I1.I3.I2 term PP end
    gate I1.I3.I2 term F5 end
    gate I1.I3.I2 term F3 end
    gate I1.I3.I2 term F1 end
    gate I1.I3.I2 term NS end
    gate I1.I3.I2 term D1 end
    gate I1.I3.I2 term C1 end
    gate I1.I3.I2 term B1 end
    gate I1.I3.I2 term MS end
    gate I1.I3.I2 term OS end
    gate I1.I3.I2 term A5 end
    gate I1.I3.I2 term A3 end
    gate I1.I3.I2 term A1 end
    gate I1.I2.I2 term PP end
    gate I1.I2.I2 term F5 end
    gate I1.I2.I2 term F3 end
    gate I1.I2.I2 term F1 end
    gate I1.I2.I2 term NS end
    gate I1.I2.I2 term D1 end
    gate I1.I2.I2 term C1 end
    gate I1.I2.I2 term B1 end
    gate I1.I2.I2 term MS end
    gate I1.I2.I2 term OS end

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亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频
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