/* Verilog Model Created from SCS Schematic example_en_16bit_s.sch 
   Aug 14, 2003 12:15 */

/* Automatically generated by hvveri version 9.5 Release Build2 */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_en_16bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
 output [15:0] count_out;
input enable_in;
parameter syn_macro = 1;
wire [15:0] count;
wire [15:0] count_reg;
wire enable_reg;
wire enable;
wire clear;
wire clk;

counter_en_16bit_s I9 ( .clear(clear), .clk(clk), .count({ count[15:0] }),
                     .enable(enable_reg) );
rg16_25um I1 ( .CLK(clk), .D({ count[15:0] }), .Q({ count_reg[15:0] }) );
dff_2 I2 ( .CLK(clk), .D1(enable), .D2(enable), .Q1(enable_reg) );
opad16_25um I3 ( .A({ count_reg[15:0] }), .P({ count_out[15:0] }) );
inpad_25um I4 ( .P(enable_in), .Q(enable) );
ckpad_25um I5 ( .P(clear_in), .Q(clear) );
ckpad_25um I6 ( .P(clk_in), .Q(clk) );

endmodule // example_en_16bit_s


`ifdef counter_en_16bit_s
`else
`define counter_en_16bit_s
module counter_en_16bit_s( clear , clk, enable, count );
input clear, clk;
 output [15:0] count;
input enable;
parameter syn_macro = 1;
wire enable_1;
wire enable_2;

counter_en_8bit_ii_s I8 ( .clear(clear), .clk(clk), .count({ count[15:8] }),
                       .enable(enable), .enable_1(enable_1),
                       .enable_2(enable_2) );
counter_en_8bit_i_s I9 ( .clear(clear), .clk(clk), .count({ count[7:0] }),
                      .enable(enable), .enable_2_r(enable_2),
                      .fo_enable_r(enable_1) );

endmodule // counter_en_16bit_s

`endif

`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK;
 input [15:0] D;
 output [15:0] Q;
parameter syn_macro = 1;

dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg16_25um

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK, D1, D2;
output Q1, Q2;
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1) );

endmodule // dff_2

`endif

`ifdef opad16_25um
`else
`define opad16_25um
module opad16_25um( A , P );
 input [15:0] A;
 output [15:0] P;
parameter syn_macro = 1;

outpad_25um I1 ( .A(A[0]), .P(P[0]) );
outpad_25um I2 ( .A(A[1]), .P(P[1]) );
outpad_25um I3 ( .A(A[2]), .P(P[2]) );
outpad_25um I4 ( .A(A[3]), .P(P[3]) );
outpad_25um I5 ( .A(A[4]), .P(P[4]) );
outpad_25um I6 ( .A(A[5]), .P(P[5]) );
outpad_25um I7 ( .A(A[6]), .P(P[6]) );
outpad_25um I8 ( .A(A[7]), .P(P[7]) );
outpad_25um I9 ( .A(A[8]), .P(P[8]) );
outpad_25um I10 ( .A(A[9]), .P(P[9]) );
outpad_25um I11 ( .A(A[10]), .P(P[10]) );
outpad_25um I12 ( .A(A[11]), .P(P[11]) );
outpad_25um I13 ( .A(A[12]), .P(P[12]) );
outpad_25um I14 ( .A(A[13]), .P(P[13]) );
outpad_25um I15 ( .A(A[14]), .P(P[14]) );
outpad_25um I16 ( .A(A[15]), .P(P[15]) );

endmodule // opad16_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef counter_en_8bit_ii_s
`else
`define counter_en_8bit_ii_s
module counter_en_8bit_ii_s( clear , clk, enable, enable_1, enable_2, count,
                             enable_3_r, enable_4_r );
input clear, clk;
 output [7:0] count;
input enable, enable_1, enable_2;
output enable_3_r, enable_4_r;
parameter syn_macro = 1;
wire enable_in2_a;
wire enable_in1_a;
supply1 vcc;
supply0 gnd;

counter_en_4bit_s I16 ( .clear(clear), .clk(clk), .enable(enable_in1_a),
                     .qa_r(count[3]), .qb_r(count[2]), .qc_r(count[1]),
                     .qd_r(count[0]) );
counter_en_4bit_s I17 ( .clear(clear), .clk(clk), .enable(enable_in2_a),
                     .qa_r(count[7]), .qb_r(count[6]), .qc_r(count[5]),
                     .qd_r(count[4]) );
super_logic I15 ( .A1(count[3]), .A2(gnd), .A3(count[2]), .A4(gnd), .A5(count[1]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(count[0]),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(enable_1), .F2(gnd),
               .F3(enable_2), .F4(gnd), .F5(enable), .F6(gnd),
               .FZ(enable_in1_a), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd),
               .OP(vcc), .OS(gnd), .PP(gnd), .PS(gnd), .QC(clk), .QR(clear),
               .QS(gnd), .QZ(enable_3_r) );
super_logic I12 ( .A1(count[7]), .A2(gnd), .A3(count[6]), .A4(gnd), .A5(count[5]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(count[4]),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(enable), .F2(gnd),
               .F3(enable_in1_a), .F4(gnd), .F5(enable_3_r), .F6(gnd),
               .FZ(enable_in2_a), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd),
               .OP(vcc), .OS(gnd), .PP(gnd), .PS(gnd), .QC(clk), .QR(clear),
               .QS(gnd), .QZ(enable_4_r) );

endmodule // counter_en_8bit_ii_s

`endif

`ifdef counter_en_8bit_i_s
`else
`define counter_en_8bit_i_s
module counter_en_8bit_i_s( clear , clk, enable, count, enable_2_r, fo_enable_r );
input clear, clk;
 output [7:0] count;
input enable;
output enable_2_r, fo_enable_r;
parameter syn_macro = 1;
wire enable_1_a;
wire enable_buf_a;
supply1 vcc;
supply0 gnd;

counter_en_4bit_s I20 ( .clear(clear), .clk(clk), .enable(enable_buf_a),
                     .qa_r(count[3]), .qb_r(count[2]), .qc_r(count[1]),
                     .qd_r(count[0]) );
counter_en_4bit_s I21 ( .clear(clear), .clk(clk), .enable(enable_1_a),
                     .qa_r(count[7]), .qb_r(count[6]), .qc_r(count[5]),
                     .qd_r(count[4]) );
super_logic I19 ( .A1(count[7]), .A2(gnd), .A3(count[6]), .A4(gnd), .A5(count[5]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd), .D1(count[4]),
               .D2(gnd), .E1(gnd), .E2(gnd), .F1(enable), .F2(gnd), .F3(vcc),
               .F4(gnd), .F5(vcc), .F6(gnd), .FZ(enable_buf_a), .MP(gnd),
               .MS(gnd), .NP(gnd), .NS(gnd), .OP(vcc), .OS(gnd), .PP(gnd),
               .PS(gnd), .QC(clk), .QR(clear), .QS(gnd), .QZ(enable_2_r) );
super_logic I14 ( .A1(count[3]), .A2(gnd), .A3(count[2]), .A4(gnd), .A5(count[1]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd), .D1(count[0]),
               .D2(gnd), .E1(vcc), .E2(count[0]), .F1(fo_enable_r), .F2(gnd),
               .F3(enable), .F4(gnd), .F5(vcc), .F6(gnd), .FZ(enable_1_a),
               .MP(gnd), .MS(gnd), .NP(gnd), .NS(enable_buf_a), .OP(vcc),
               .OS(gnd), .PP(gnd), .PS(gnd), .QC(clk), .QR(clear), .QS(gnd),
               .QZ(fo_enable_r) );

endmodule // counter_en_8bit_i_s

`endif

`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                    F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
                    QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1, ql_pack = 1;
parameter ql_gate = `LOGIC;

super_cell I2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ),
             .B1(B1), .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1),
             .E2(E2), .F1(F1), .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6),
             .FZ(FZ), .MP(MP), .MS(MS), .NP(NP), .NS(NS), .NZ(NZ), .OP(OP),
             .OS(OS), .OZ(OZ), .PP(PP), .PS(PS), .Q2Z(Q2Z), .QC(QC), .QR(QR),
             .QS(QS), .QZ(QZ) );

endmodule // super_logic

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter syn_macro = 1;
parameter ql_frag = 1;
 wire EQMUX_Z, OQMUX_Z; 
 reg EQZ, OQQ, IQQ; 
 assign #1 EQMUX_Z = ESEL ? IE : EQZ; 
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ; 
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz; 
 assign #1 IZ = IP; 

  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      EQZ <= #1 1'b0;
    else if (EQE)
      EQZ <= #1 IE; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      IQQ <= #1 1'b0; 
    else if (IQE) 
      IQQ <= #1 IP; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR) 
      OQQ <= #1 1'b0; 
    else 
      OQQ <= #1 OQI; 

endmodule // eio_cell

`endif

`ifdef ckcell_25um
`else
`define ckcell_25um
module ckcell_25um( IP , IC );
output IC;
input IP;
parameter syn_macro = 1;
parameter ql_frag = 1;
 assign #1 IC = IP;

endmodule // ckcell_25um

`endif

`ifdef counter_en_4bit_s
`else
`define counter_en_4bit_s
module counter_en_4bit_s( clear , clk, enable, qa_r, qb_r, qc_r, qd_r );
input clear, clk, enable;
output qa_r, qb_r, qc_r, qd_r;
parameter syn_macro = 1;
wire BCD_a;
wire ABCDE_a;
wire ED_a;
supply0 GND;
supply1 VCC;

super_logic I1 ( .A1(BCD_a), .A2(GND), .A3(ED_a), .A4(GND), .A5(qa_r), .A6(GND),
              .AZ(ABCDE_a), .B1(ED_a), .B2(qc_r), .C1(qc_r), .C2(ED_a),
              .D1(qb_r), .D2(GND), .E1(VCC), .E2(qb_r), .F1(qc_r), .F2(GND),
              .F3(qd_r), .F4(GND), .F5(VCC), .F6(GND), .MP(GND), .MS(qc_r),
              .NP(enable), .NS(GND), .OP(GND), .OS(GND), .PP(GND), .PS(GND),
              .Q2Z(qb_r), .QC(clk), .QR(clear), .QS(GND), .QZ(qc_r) );
super_logic I2 ( .A1(enable), .A2(GND), .A3(qd_r), .A4(GND), .A5(VCC), .A6(GND),
              .AZ(ED_a), .B1(qa_r), .B2(GND), .C1(VCC), .C2(qa_r), .D1(enable),
              .D2(qd_r), .E1(qd_r), .E2(enable), .F1(qb_r), .F2(GND), .F3(qc_r),
              .F4(GND), .F5(qd_r), .F6(GND), .FZ(BCD_a), .MP(enable), .MS(GND),
              .NP(GND), .NS(qd_r), .OP(GND), .OS(GND), .PP(GND), .PS(GND),
              .Q2Z(qd_r), .QC(clk), .QR(clear), .QS(GND), .QZ(qa_r) );

endmodule // counter_en_4bit_s

`endif

`ifdef super_cell
`else
`define super_cell
module super_cell( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                   F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC, QR,
                   QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1, ql_pack = 1;
parameter ql_frag = 1;
 wire TOPMUX_Z, MIDMUX_Z, BOTMUX_Z, FFMUX_Z, CLKMUX_Z; 
 wire MZ; 
 reg QZ, Q2Z; 
 
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6; 
 assign #1 TOPMUX_Z = OP ? AZ : OS; 
 assign #1 MZ = MIDMUX_Z ? (C1 & ~C2) : (B1 & ~B2); 
 assign #1 MIDMUX_Z = MP ? FZ : MS; 
 assign #1 NZ = BOTMUX_Z ? (E1 & ~E2) : (D1 & ~D2); 
 assign #1 BOTMUX_Z = NP ? FZ : NS; 
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6; 
 assign #1 OZ = TOPMUX_Z ? NZ : MZ; 
 assign #1 FFMUX_Z = PP ? PS : NZ; 
`ifdef synthesis 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
     else 
        #1 QZ = OZ; 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
     else 
        #1 Q2Z = FFMUX_Z; 
`else 
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 QZ = OZ; 
  always @ (QR or QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 Q2Z = FFMUX_Z; 
  always @ (QR or QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
`endif 

endmodule // super_cell

`endif