else
        dummy_read_en <= dummy_read_en;
   end

   // ctrl_Dummyread_Start signal generation to the data path module
   always @ (posedge clk_0) begin
      if (rst_r)
        ctrl_Dummyread_Start_r1 <= 1'b0;
      else if ((dummy_read_en == 1'b1) && (cas_count == 3'b000))
        ctrl_Dummyread_Start_r1 <= 1'b1;
      else if (phy_Dly_Slct_Done == 1'b1)
        ctrl_Dummyread_Start_r1 <= 1'b0;
      else
        ctrl_Dummyread_Start_r1 <= ctrl_Dummyread_Start_r1;
   end

   // register ctrl_Dummyread_Start signal
   always @ (posedge clk_0) begin
      if (rst_r) begin
         ctrl_Dummyread_Start_r2 <= 1'b0;
         ctrl_Dummyread_Start_r3 <= 1'b0;
         ctrl_Dummyread_Start_r4 <= 1'b0;
         ctrl_Dummyread_Start <= 1'b0;
      end
      else begin
         ctrl_Dummyread_Start_r2 <=  ctrl_Dummyread_Start_r1;
         ctrl_Dummyread_Start_r3 <=  ctrl_Dummyread_Start_r2;
         ctrl_Dummyread_Start_r4 <=  ctrl_Dummyread_Start_r3;
         ctrl_Dummyread_Start <=  ctrl_Dummyread_Start_r4;
      end
   end // always @ (posedge clk_0)

   // read_wait/write_wait to idle count
   // the state machine waits for 15 clock cycles in the write wait state for
   //  any wr/rd commands to be issued. If no commands are issued in 15 clock
   // cycles, the statemachine issues enters the idle state and stays in the
   // idle state until an auto refresh is required.

   always @ (posedge clk_0) begin
      if (rst_r)
        idle_cnt[3:0] <= 4'b0000;
      else if (read_write_state)
        idle_cnt[3:0] <= 4'b1111 ;
      else if (idle_cnt[3:0] != 4'b0000)
        idle_cnt[3:0] <= idle_cnt[3:0] - 1;
      else
        idle_cnt[3:0] <= 4'b0000;
   end

   always @ (posedge clk_0) begin
      if (rst_r)
        cas_check_count[3:0] <= 4'b0000;
      else if (first_read_state_r2 || pattern_read_state_1_r2)
        cas_check_count[3:0] <= (CAS_LATENCY_VALUE - 1);
      else if (cas_check_count[3:0] != 4'b0000)
        cas_check_count[3:0] <= cas_check_count[3:0] - 1;
      else
        cas_check_count[3:0] <= 4'b0000;
   end

   always @ (posedge clk_0) begin
      if (rst_r) begin
         rdburst_cnt[2:0] <= 3'b000;
         ctrl_RdEn_r <= 1'b0;
      end
      else if ((cas_check_count == 4'b0001) && (!burst_read_state_r3)) begin
         rdburst_cnt[2:0] <= burst_cnt[2:0];
         ctrl_RdEn_r <= 1'b1;
      end
      else if(burst_read_state_r3 || pattern_read_state_r3) begin
        if(burst_cnt == 3'd4)
          rdburst_cnt[2:0] <= CAS_LATENCY_VALUE + burst_cnt/2;
        else if (burst_cnt == 3'd2)
          rdburst_cnt[2:0] <= CAS_LATENCY_VALUE;
        else
          rdburst_cnt[2:0] <= CAS_LATENCY_VALUE - burst_cnt;
      if(burst_read_state_r3)
        ctrl_RdEn_r <= 1'b1;
      end
      else if (rdburst_cnt[2:0] != 3'b000) begin
         rdburst_cnt[2:0] <= rdburst_cnt[2:0] - 1'b1;
         if(rdburst_cnt == 3'd1)
           ctrl_RdEn_r <= 1'b0;
      end
      else
         rdburst_cnt[2:0] <= 3'b000;
   end

   always@(posedge clk_0) begin
      if(rst_r)
        ctrl_RdEn_r1 <= 1'b0;
      else
        ctrl_RdEn_r1 <= ctrl_RdEn_r;
   end

   assign ctrl_RdEn = (registered_dimm) ? ctrl_RdEn_r1 : ctrl_RdEn_r;


   // write address FIFO read enable signals

   assign af_rden = (read_write_state || ((state == MODE_REGISTER_WAIT) & LMR_r &
                                          !mrd_count) ||((state == PRECHARGE )&&
                                                         PRE_r) ||
                     ((state == AUTO_REFRESH) && REF_r) || ((state == ACTIVE )&& ACT_r));


   // write data fifo read enable
   always @ (posedge clk_0) begin
      if (rst_r)
        wdf_rden_r  <= 1'b0;
      else if (write_state )
        wdf_rden_r  <= 1'b1;
      else
        wdf_rden_r  <= 1'b0;
   end

   always @ (posedge clk_0) begin
      if (rst_r) begin
         wdf_rden_r2 <= 1'b0;
         wdf_rden_r3 <= 1'b0;
         wdf_rden_r4 <= 1'b0;
      end
      else begin
         wdf_rden_r2 <= wdf_rden_r;
         wdf_rden_r3 <= wdf_rden_r2;
         wdf_rden_r4 <= wdf_rden_r3;
      end // else: !if(rst_r)
   end // always @ (posedge clk_0)

   // Read enable to the data fifo
   always @ (burst_cnt or wdf_rden_r or wdf_rden_r2 or wdf_rden_r3 or wdf_rden_r4 ) begin
      if (burst_cnt == 3'b001)
        ctrl_Wdf_RdEn_r <= (wdf_rden_r ) ;
      else if (burst_cnt == 3'b010)
        ctrl_Wdf_RdEn_r <= (wdf_rden_r | wdf_rden_r2) ;
      else if (burst_cnt == 3'b100)
             ctrl_Wdf_RdEn_r <= (wdf_rden_r | wdf_rden_r2 | wdf_rden_r3 | wdf_rden_r4) ;
      else ctrl_Wdf_RdEn_r <= 1'b0;
   end

   always@(posedge clk_0) begin
      if(rst_r)
        ctrl_Wdf_RdEn_r1 <= 1'b0;
      else
        ctrl_Wdf_RdEn_r1 <= ctrl_Wdf_RdEn_r;
   end

   assign ctrl_Wdf_RdEn = (registered_dimm) ? ctrl_Wdf_RdEn_r1 : ctrl_Wdf_RdEn_r;

   always @ (posedge clk_0) begin
      if(rst_r)
        dummy_write_flag <= 1'b0;
      else
        dummy_write_flag <= phy_Dly_Slct_Done && ~(comp_done);
   end

   always @ (posedge clk_0) begin
      if (rst_r)
        state <= IDLE;
      else
        state <= next_state;
   end

   always @ (posedge clk_0) begin
      if (rst_r)
        init_state <= INIT_IDLE;
      else
        init_state <= init_next_state;
   end

   always@(posedge clk_0) begin
      if(rst_r)
        count5 <= 5'b00000;
      else begin
         case (init_state)
           INIT_PRECHARGE_WAIT, INIT_MODE_REGISTER_WAIT, INIT_AUTO_REFRESH_WAIT,
           INIT_DUMMY_WRITE_READ, INIT_PATTERN_READ_WAIT,INIT_DUMMY_READ_WAIT,
           INIT_DUMMY_ACTIVE_WAIT :
             begin
                count5 <= count5 + 1;
             end

           default:
             count5 <= 5'b00000;
         endcase
      end
   end

   //Initialization state machine
   always @ (*) begin
      init_next_state = init_state;
      case (init_state)
        INIT_IDLE : begin
           if (init_memory && done_200us == 1'b1) begin
              case (init_count )
                4'h0 : init_next_state = INIT_INITCOUNT_200;
                4'h1 : init_next_state = INIT_PRECHARGE;
                4'h2 :init_next_state = INIT_LOAD_MODE_REG_ST;
                4'h3 :init_next_state = INIT_LOAD_MODE_REG_ST;
                4'h4 :init_next_state = INIT_INITCOUNT_200;
                4'h5 :init_next_state = INIT_PRECHARGE;
                4'h6 :init_next_state = INIT_AUTO_REFRESH;
                4'h7 :init_next_state = INIT_AUTO_REFRESH;
                4'h8 :init_next_state = INIT_LOAD_MODE_REG_ST;
                4'h9 :  begin
                   if( (chip_cnt < `no_of_cs-1))
                     init_next_state = INIT_DEEP_MEMORY_ST;
                   else  if (`Phy_Mode  && count_200cycle_done_r)
                     init_next_state = INIT_DUMMY_READ_CYCLES;
                   else
                     init_next_state = INIT_IDLE;
                end
                4'hA :  begin
                   if (phy_Dly_Slct_Done) begin
                      init_next_state = INIT_IDLE;
                   end
                end
                default: init_next_state = INIT_IDLE;

              endcase // case(init_count )
           end
        end // case: `idle

        INIT_DEEP_MEMORY_ST :    init_next_state = INIT_IDLE;

        INIT_INITCOUNT_200 : init_next_state = INIT_INITCOUNT_200_WAIT;

        INIT_INITCOUNT_200_WAIT     : begin
           if (count_200cycle_done_r)
             init_next_state = INIT_IDLE;
           else
             init_next_state = INIT_INITCOUNT_200_WAIT;
        end

        INIT_DUMMY_READ_CYCLES  : init_next_state = INIT_DUMMY_ACTIVE;


        INIT_DUMMY_ACTIVE       : init_next_state = INIT_DUMMY_ACTIVE_WAIT;

        INIT_DUMMY_ACTIVE_WAIT  : begin
           if (count5 == cntnext)
             if(dummy_write_flag)
               init_next_state = INIT_DUMMY_WRITE1;
             else
               init_next_state = INIT_DUMMY_FIRST_READ;
           else
             init_next_state = INIT_DUMMY_ACTIVE_WAIT;
        end

        INIT_DUMMY_FIRST_READ  :
           init_next_state = INIT_DUMMY_READ_WAIT;

        INIT_DUMMY_READ        : begin
           if((burst_cnt == 3'd1) && (~phy_Dly_Slct_Done))
             init_next_state = INIT_DUMMY_READ;
           else
             init_next_state = INIT_DUMMY_READ_WAIT;
        end

        INIT_DUMMY_READ_WAIT    : begin
           if (phy_Dly_Slct_Done) begin
              if(count5 == cntnext)
                if(auto_ref == 1'b1)
                  init_next_state = INIT_PRECHARGE;
                else
                  init_next_state = INIT_DUMMY_WRITE1;
              else
                init_next_state = INIT_DUMMY_READ_WAIT;
           end
           else
             init_next_state = INIT_DUMMY_READ;
        end

        INIT_DUMMY_WRITE1 :
          begin
             if ( burst_cnt == 3'd1 )
               init_next_state = INIT_DUMMY_WRITE2;
             else
               init_next_state = INIT_DUMMY_WRITE_READ;
          end

        INIT_DUMMY_WRITE2 : init_next_state = INIT_DUMMY_WRITE_READ;

        INIT_DUMMY_WRITE_READ:
          begin
             if (count5 == cntnext)
               init_next_state = INIT_PATTERN_READ1;
             else
               init_next_state = INIT_DUMMY_WRITE_READ;
          end

        INIT_PATTERN_READ1 :
          begin
             if ( burst_cnt == 3'd1 )
               init_next_state = INIT_PATTERN_READ2;
             else
               init_next_state = INIT_PATTERN_READ_WAIT;
          end

        INIT_PATTERN_READ2 :
          init_next_state = INIT_PATTERN_READ_WAIT;

        INIT_PATTERN_READ_WAIT:
          begin
             if(comp_done)
               init_next_state = INIT_PRECHARGE;
             else
               init_next_state = INIT_PATTERN_READ_WAIT;
          end

        INIT_PRECHARGE  :init_next_state = INIT_PRECHARGE_WAIT;


        INIT_PRECHARGE_WAIT     : begin
           if (count5 == cntnext)
             if (auto_ref && dummy_write_flag)
               init_next_state = INIT_AUTO_REFRESH;
             else
               init_next_state = INIT_IDLE;
           else
             init_next_state = INIT_PRECHARGE_WAIT;
        end // case

        INIT_LOAD_MODE_REG_ST      : init_next_state = INIT_MODE_REGISTER_WAIT;

        INIT_MODE_REGISTER_WAIT : begin
           if (count5 == cntnext)
             init_next_state = INIT_IDLE;
           else
             init_next_state = INIT_MODE_REGISTER_WAIT;

        end

        INIT_AUTO_REFRESH       :init_next_state = INIT_AUTO_REFRESH_WAIT;

        INIT_AUTO_REFRESH_WAIT  : begin
           if ((count5 == cntnext) && (phy_Dly_Slct_Done))
             init_next_state = INIT_DUMMY_ACTIVE;
           else if (count5 == cntnext)
             init_next_state = INIT_IDLE;
           else
             init_next_state = INIT_AUTO_REFRESH_WAIT;
        end
      endcase
   end

   //main controller state machine
   always @ (*) begin
      next_state = state;
      case (state)
        IDLE : begin
           if ((conflict_detect_r || LMR_PRE_REF_ACT_cmd_r || auto_ref) &&
               ras_count == 4'b0000 && init_done_int)
             next_state = PRECHARGE;
           else if ((WR_r  || RD_r ) && (ras_count == 4'b0000)) begin
              next_state = ACTIVE;
           end
        end

        LOAD_MODE_REG_ST      : next_state = MODE_REGISTER_WAIT;

        MODE_REGISTER_WAIT : begin
           if (mrd_count == 1'b0)
             next_state = IDLE;
           else
             next_state = MODE_REGISTER_WAIT;
        end

        PRECHARGE          :next_state = PRECHARGE_WAIT;

        PRECHARGE_WAIT     : begin
           if (rp_count == 3'b000) begin
              if (auto_ref || REF_r) begin
                 next_state = AUTO_REFRESH;
              end else if (LMR_r) begin
                 next_state = LOAD_MODE_REG_ST;
              end else if (conflict_detect_r || ACT_r) begin
                 next_state = ACTIVE;
              end else  begin
                 next_state = IDLE;
              end
           end else begin
              next_state = PRECHARGE_WAIT;
           end
        end

        AUTO_REFRESH       :next_state = AUTO_REFRESH_WAIT;

        AUTO_REFRESH_WAIT  : begin