USB接口控制器參考設(shè)計(jì),xilinx提供VHDL代碼 usb xilinx vhdl
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標(biāo)簽：
xilinx
VHDL
USB
us
上傳時(shí)間：
2013-10-12
上傳用戶：windgate
介紹了一種10M/ 100M 以太網(wǎng)控制器的實(shí)現(xiàn)方法,該控制器以FIFO 作為幀緩存,通過程序設(shè)計(jì)實(shí)現(xiàn)10M/ 100M 自適應(yīng),設(shè)計(jì)中采用WS 接口,提高了設(shè)計(jì)的靈活行,可以實(shí)現(xiàn)與其他SOC 的互連[1 ] ,該設(shè)計(jì)采用VerilogHDL 硬件描述語言編程,基于ISE 開發(fā)環(huán)境,在Xilinx 公司的Spartan2 Ⅲ系列FPGA XC3S1000242FT256C 上實(shí)現(xiàn)。關(guān)鍵詞:以太網(wǎng)MAC;10M/ 100M; FPGA ;VerilogHDL
標(biāo)簽：
FPGA
100
10
以太網(wǎng)控制器
上傳時(shí)間：
2013-10-18
上傳用戶：liglechongchong
