Singular value decomposition filter for speckle reduction in adaptive ultrasound imagingHasegawa_2019_Jpn._J._Appl._Phys._58_SGGE06
標(biāo)簽： decomposition ultrasound reduction Singular adaptive speckle imaging filter value for
上傳時(shí)間： 2020-06-04
上傳用戶：mengdeming
A power semiconductor module is basically a power circuit of different materials assembled together using hybrid technology, such as semiconduc- tor chip attachment, wire bonding, encapsulation, etc. The materials involved cover a wide range from insulators, conductors, and semiconduc- tors to organics and inorganics. Since these materials all behave differently under various environmental, electrical, and thermal stresses, proper selec- tion of these materials and the assembly processes are critical. In-depth knowledge of the material properties and the processing techniques is there- fore required to build a high-performance and highly reliable power module.
標(biāo)簽： Manufacture Electronic Modules Design Power
上傳時(shí)間： 2020-06-07
上傳用戶：shancjb
stract With global drivers such as better energy consumption, energy efficiency and reduction of greenhouse gases, CO 2 emission reduction has become key in every layer of the value chain. Power Electronics has definitely a role to play in these thrilling challenges. From converters down to compound semiconductors, innovation is leading to breakthrough technologies. Wide BandGap, Power Module Packaging, growth of Electric Vehicle market will game change the overall power electronic industry and supply chain. In this presentation we will review power electronics trends, from technologies to markets.
標(biāo)簽： Electronics Materials Power WBG for
上傳時(shí)間： 2020-06-07
上傳用戶：shancjb
lm75A溫度數(shù)字轉(zhuǎn)換器 FPGA讀寫實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學(xué)習(xí)設(shè)計(jì)參考。LM75A 是一個(gè)使用了內(nèi)置帶隙溫度傳感器和模數(shù)轉(zhuǎn)換技術(shù)的溫度數(shù)字轉(zhuǎn)換器。它也是一個(gè)溫度檢測器，可提供一個(gè)過熱檢測輸出。LM75A 包含許多數(shù)據(jù)寄存器：配置寄存器用來存儲器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊(duì)列等（在功能描述一節(jié)中有詳細(xì)描述）；溫度寄存器（Temp），用來存儲讀取的數(shù)字溫度；設(shè)定點(diǎn)寄存器（Tos & Thyst），用來存儲可編程的過熱關(guān)斷和滯后限制，器件通過2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個(gè)開漏輸出（OS），當(dāng)溫度超過編程限制的值時(shí)該輸出有效。LM75A 有3 個(gè)可選的邏輯地址管腳，使得同一總線上可同時(shí)連接8個(gè)器件而不發(fā)生地址沖突。LM75A 可配置成不同的工作條件。它可設(shè)置成在正常工作模式下周期性地對環(huán)境溫度進(jìn)行監(jiān)控或進(jìn)入關(guān)斷模式來將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊(duì)列和設(shè)定點(diǎn)限制可編程，為了激活OS 輸出，故障隊(duì)列定義了許多連續(xù)的故障。溫度寄存器通常存放著一個(gè)11 位的二進(jìn)制數(shù)的補(bǔ)碼，用來實(shí)現(xiàn)0.125℃的精度。這個(gè)高精度在需要精確地測量溫度偏移或超出限制范圍的應(yīng)用中非常有用。正常工作模式下，當(dāng)器件上電時(shí)，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時(shí)，LM75A就可用作一個(gè)具有以上預(yù)定義溫度設(shè)定點(diǎn)的獨(dú)立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
標(biāo)簽： lm75a 數(shù)字轉(zhuǎn)換器 fpga verilog
上傳時(shí)間： 2021-10-27
上傳用戶：
FPGA采樣AD9238數(shù)據(jù)并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號為 AN9238，最大采樣率 65Mhz，精度為12 位。實(shí)驗(yàn)中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個(gè)數(shù)字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時(shí)間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實(shí)驗(yàn) Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實(shí)驗(yàn)簡介在前面的實(shí)驗(yàn)中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實(shí)驗(yàn)將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實(shí)驗(yàn)如果通過液晶屏顯示，需要有液晶屏模塊。2 實(shí)驗(yàn)原理在前面的實(shí)驗(yàn)中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實(shí)驗(yàn)將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠(yuǎn)遠(yuǎn)不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時(shí)序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標(biāo)簽： fpga
上傳時(shí)間： 2021-10-27
上傳用戶：
基于TMS320F2812 光伏并網(wǎng)發(fā)電模擬裝置PROTEL設(shè)計(jì)原理圖+PCB+軟件源碼+WORD論文文檔,硬件采用2層板設(shè)計(jì)，PROTEL99SE 設(shè)計(jì)的工程文件，包括完整的原理圖和PCB文件，可以做為你的學(xué)習(xí)設(shè)計(jì)參考。 摘要：本文實(shí)現(xiàn)了一個(gè)基于TMS320F2812 DSP芯片的光伏并網(wǎng)發(fā)電模擬裝置，采用直流穩(wěn)壓源和滑動(dòng)變阻器來模擬光伏電池。通過TMS320F2812 DSP芯片ADC模塊實(shí)時(shí)采樣模擬電網(wǎng)電壓的正弦參考信號、光伏電池輸出電壓、負(fù)載電壓電流反饋信號等。經(jīng)過數(shù)據(jù)處理后，用PWM模塊產(chǎn)生實(shí)時(shí)的SPWM 波，控制MOSFET逆變?nèi)珮蜉敵稣也ā１疚挠肞I控制算法實(shí)現(xiàn)了輸出信號對給定模擬電網(wǎng)電壓的正弦參考信號的頻率和相位跟蹤，用恒定電壓法實(shí)現(xiàn)了光伏電池最大功率點(diǎn)跟蹤（MPPT），從而達(dá)到模擬并網(wǎng)的效果。另外本裝置還實(shí)現(xiàn)了光伏電池輸出欠壓、負(fù)載過流保護(hù)功能以及光伏電池輸出欠壓、過流保護(hù)自恢復(fù)功能、聲光報(bào)警功能、孤島效應(yīng)的檢測、保護(hù)與自恢復(fù)功能。系統(tǒng)測試結(jié)果表明本設(shè)計(jì)完全滿定設(shè)計(jì)要求。關(guān)鍵詞：光伏并網(wǎng)，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, outputting voltage of photovoltaic, feedback outputting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge output sine wave. We realized that the output voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目錄引言 11. 方案論證 11.1. 總體介紹 11.2. 光伏電池模擬裝置 11.3. DC-AC逆變橋 11.4. MOSFET驅(qū)動(dòng)電路方案 21.5. 逆變電路的變頻控制方案 22. 理論分析與計(jì)算 22.1. SPWM產(chǎn)生 22.1.1. 規(guī)則采樣法 22.1.2. SPWM 脈沖的計(jì)算公式 32.1.3. SPWM 脈沖計(jì)算公式中的參數(shù)計(jì)算 32.1.4. TMS320F2812 DSP控制器的事件管理單元 42.1.5. 軟件設(shè)計(jì)方法 62.2. MPPT的控制方法與參數(shù)計(jì)算 72.3. 同頻、同相的控制方法和參數(shù)計(jì)算 8
標(biāo)簽： tms320f2812 光伏 并網(wǎng)發(fā)電 模擬 protel pcb
上傳時(shí)間： 2021-11-02
上傳用戶：
CH340C+RT9013+MINI USB接口板 AD設(shè)計(jì)硬件原理圖+PCB文件,ALTIUM設(shè)計(jì)的2層板設(shè)計(jì)，包括完整的原理圖和PCB文件，主要器件如下：Library Component Count : 12Name Description----------------------------------------------------------------------------------------------------CAP CapacitorCC2640EM CC2630 ModuleCH340 CH340 USB 2 UARTCON11 Connector 11pinsCON12 Connector 12pinsCON3X2 Connector 5*2LED LEDRES ResistorRT9013 RT9013 3.3VSWITCH switch 6*6USB1 USB ConnectorsXDS110-Lte XDS110-Lite Target Interface
標(biāo)簽： ch340c rt9013 usb 接口 ad設(shè)計(jì)
上傳時(shí)間： 2021-11-24
上傳用戶：canderile
STM32L475開發(fā)板PDF原理圖+AD集成3D封裝庫+主要器件技術(shù)手冊，集成封裝庫型號列表如下：Library Component Count : 44Name Description----------------------------------------------------------------------------------------------------ANT-2.4G ANT,2.4G,PCB天線ATK-TEST-1*4-2.54mm 測試點(diǎn)ATK_MODULE 單排母,1*6,2.54mmBEEP 3.3V有源蜂鳴器BUTTON_DIP3 撥動(dòng)開關(guān)SS-12F44C-0402-SMD C-0603-SMD C-CAP-SMD-220uF/10V C-CEP-220uF/16V D-1N4148 Header-1*3-2.54mm 單排針-2.54mmHeader-2*10-2.54mm 雙排針-2.54mmHeader-2*2-2.54mm 雙排針-2.54mmHeader-2*3-2.54mm 雙排針-2.54mmHeader-2*4-2.54mm 雙排座-2.54mmIR-LED 1206紅外發(fā)射管（側(cè)）IR-LF0038GKLL-1 紅外接收管SMDJ-MICRO-USB-5S Micro USB 5.9有柱腳長1.25加長針L-0420-4.7uH 電感,4.7uH,3ALCD-TFT-H13TS38A LCD,TFT,1.3'240*240,禹龍LED-0603-RED 發(fā)光二極管-紅色LED-RGB-1615-0603 RGB,共陽,1615,0603MIC-6022 MICMotor-SMD 電機(jī),SMDPhone-3-M 耳機(jī)座,三節(jié)R-0402-SMD 貼片電阻R-0805-SMD 貼片電阻RT9193-3.3S-KEY-SMD-324225 KEY,SMD,324225S8050-SMD SD-MICRO-TF SD,MICRO,TFU-AHT10 Sensor,溫濕度傳感器U-AP3216C Sensor.光照/距離U-AP6181 WIFI Module,SDIOU-ES8388 AUDIO,2-ch DAC,2-ch ADCU-ICM-20608 三軸陀螺儀/三軸加速度計(jì),U-L9110S 電機(jī)驅(qū)動(dòng),800mAU-RT9013-3.3 LDO,500mAU-STM32F103C8T6 U-STM32L475VET6 MCU,LQFP100,512K FLASH,128K RAMU-W25Q128 SPI FLASH,16MY-12M-SMD 晶振 - 12M貼片Y-3215-32.768K XTAL,3215,32.768KY-3215-8M XTAL,3215,8MHz
上傳時(shí)間： 2021-12-15
上傳用戶：
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時(shí)間： 2021-12-18
上傳用戶：
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