Synthesizable FIFO Model
This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
a) 參考《TMS320LF240x DSP結(jié)構(gòu)、原理及應(yīng)用》，弄清TMS320LF2407的定時(shí)器功能。
b) 測(cè)試定時(shí)器Timer1，周期中斷0.1秒，并控制燈D2閃爍時(shí)間為T(mén)s
c) 單步運(yùn)行程序，觀察發(fā)光二極管D2的發(fā)光情況。
d) 程序裝入片外，按“RUN”觀察發(fā)光二極管D2的發(fā)光情況。
