verilog hdl coding DDR sdram control for fpga
標簽： verilog control coding sdram
上傳時間： 2013-12-17
上傳用戶：wangchong
利用verlilog hdl語言編程，完成了8051內(nèi)核，非常值得學(xué)習(xí)硬件描述語言的人看看！
上傳時間： 2015-12-10
上傳用戶：erkuizhang
The Microsoft® Active Directory™ Service Interfaces (ADSI) Software Development Kit (SDK) is a client-side product, based on the Component Object Model (COM), that defines a directory service model and a set of COM interfaces that enables Microsoft Windows NT® /Windows® 2000 and Windows 95 client applications to access several network directory services.
標簽： Development Interfaces Microsoft Directory
上傳時間： 2013-12-25
上傳用戶：daguda
該代碼中有不少關(guān)于學(xué)習(xí)verilog HDL的例子,對初學(xué)者有幫助
上傳時間： 2013-12-19
上傳用戶：asdkin
圖像處理的關(guān)于Snakes : Active Contour Models算法和水平集以及GVF的幾篇文章，文章列表為： [1]Snakes Active Contour Models.pdf [2]Multiscale Active Contours.pdf [3]Snakes, shapes, and gradient vector flow.pdf [4]Motion of level sets by mean curvature I.pdf [5]Spectral Stability of Local Deformations Spectral Stability of Local Deformations.pdf [6]An active contour model for object tracking using the previous contour.pdf [7]Volumetric Segmentation of Brain Images Using Parallel Genetic AlgorithmsI.pdf [8]Segmentation in echocardiographic sequences using shape-based snake model.pdf [9]Active Contours Without Edges.pdf 學(xué)習(xí)圖像處理的人必看的幾篇文章
標簽： Contour Snakes Active Models
上傳時間： 2014-01-15
上傳用戶：wqxstar
Verilog HDL課件，有常見問題說明
上傳時間： 2013-12-21
上傳用戶：sdq_123
Verilog HDL的標準，比較詳細的語法說明
上傳時間： 2015-12-15
上傳用戶：xsnjzljj
As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.
標簽： Description enhancement activities the
上傳時間： 2015-12-15
上傳用戶：sunjet
Testbenches have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your testbench is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
標簽： Testbenches enabling integral process
上傳時間： 2014-01-25
上傳用戶：ynzfm
As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.
標簽： Description enhancement activities the
上傳時間： 2015-12-15
上傳用戶：SimonQQ
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