Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I² C™ and SPI™ ) and double ASYNCHRONOUS (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program memory make it ideal for instrumentation panels, TCP/IP enabled embedded applications as well as metering and industrial control and monitoring applications. While operating up to 40 MHz, it is also backward software and hardware compatible with the PIC18F8720.
A Linux port of the OpenBSD/FreeBSD Cryptographic Framework (OCF). This port aims to bring full ASYNCHRONOUS HW/SW crypto acceleration to the Linux kernel, OpenSwan, OpenSSL and applications using DES, 3DES, AES, MD5, SHA, PublicKey, RNGs and more.
vhdl編寫，8b—10b 編解碼器設計
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
ASYNCHRONOUS active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
ASYNCHRONOUS active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later
CRC碼產生器與校驗器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or ASYNCHRONOUS reset
基于AJAX的動態樹型結構的設計與實現
簡要介紹了一種通用的，動態樹型結構的實現方案，該方案基于ASYNCHRONOUS JavaScript and XML，結合Struts框架設計實現了結構清晰、擴展性良好的多層架構，數據存儲于數據庫，結合XML描述樹的節點信息，使得任何按預定的XML文檔描述的信息都可以通過動態樹來展現。
Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that ASYNCHRONOUS serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.
The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and verification of a digital UART (Universal
ASYNCHRONOUS Receiver & Transmitter).
The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external ASYNCHRONOUS RAM, and then send it to the computer through a serial cable
基于TMS320F28035芯片為控制核心的空間矢量異步電機變頻器 我們設計的異步電機變頻調速器以TMS320F28035芯片為控制核心，通過輸出三相PWM波控制智能功率模塊IPM驅動三相異步電機。我們使用空間矢量SVPWM算法，并對其進行了優化。采用檢測反電勢的方法省去了昂貴的光電編碼器，大大節省了成本。同時開創性的研發了自動根據運行環境調節的自適應變頻算法，使我們的變頻調速器可以在電網條件惡劣的鄉村山區工作，由此該變頻器已被一家民用水泵生產企業預訂。關鍵字 變頻器 TMS320f28035 IPM SVPWM In our design, the ASYNCHRONOUS machine inverter based on the chip of TMS320F28035 drives the three-Phase ASYNCHRONOUS machine by sending three-phase PWM waves to the IPM, which is short for the Intelligent-Power-Module. The SVPWM (space vector pulse width modulation) strategy is applied to our control algorithm and we optimize it mainly in two aspects. Firstly the inverter detects the speed by measuring the Back EMF instead of installing an expensive photoelectric encoder for costs reduction.
