The project KEIL_IODemo shows how to use memory allocation routines (malloc) and char I/O (printf, scanf) via a serial interface with the Keil ARM toolchain.
The I/O functions are adapted for the Analog Devices ADuC7000 series using the SERIAL.C module.
The example also shows the efficiency of the Keil CA ARM Compiler run-time library which is tuned for single chip systems.
UART I/O and Memory Allocation Example for GNU
The project GNU_IODemo shows how to use memory allocation routines (malloc) and char I/O (printf, scanf) via a serial interface with the GNU toolchain.
The I/O functions are adapted for the Analog Devices ADuC7000 series using the SERIAL.C module.
The example also shows the efficiency of the Keil CA ARM Compiler run-time library which is tuned for single chip systems.
dvbsnoop is a DVB/MPEG stream analyzer program.
The program can be used to sniff, monitor, debug, dump
or view DVB/MPEG/DSM-CC/MHP stream information (digital
television or data broadcasts) sent via satellite, cable
or terrestrial.
This application report introduces and describes an MP3 /AAC audio player for use with the TMS320C54x(TM) digital signal processor (DSP) devices. This audio player is based on Reference Framework Level 3 (RF3). Reference Framework for eXpressDSP(TM) Software is a start-ware for developing applications that use DSP/BIOS(TM) and the TMS320(TM) DSP AlgorithmStandard.
Basic Test Concepts
DC Parameters
AC Parameters
Functional Parameters
Device Characterization
Test Program Development
Analog Test Concepts
Test Using DSP Techniques in Testing
Noise Reduction Techniques in Testing
硬件設計指南(PDF格式)，主要包括：Low Voltage Interfaces；Grounding in Mixed Signal Systems；Digital Isolation Techniques； Power Supply Noise Reduction and Filtering； Dealing with High Speed Logic
Verilog and VHDL狀態機設計，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world examples.
I believe that technology has the capacity to fundamentally improve people’s lives, and
improve the world in which we live.We are now two years into what my company have
called the ‘Digital Decade’.We think that by 2010 a combination of hardware and software
innovation with broader social trends will change the way computing fits into our society.
Mobile technology is a central part of this vision.
