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Analog-TO-digital

  • Verilog Coding Style for Efficient Digital Design

      In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

    標(biāo)簽: Efficient Verilog Digital Coding

    上傳時(shí)間: 2013-11-22

    上傳用戶:han_zh

  • D類數(shù)字輸入放大器的簡(jiǎn)化系統(tǒng)設(shè)計(jì)

    Abstract: This application note describes a new generation of digital-input Class D audio amplifiers that achieve high PSRRperformance, comparable to traditional analog Class D amplifiers. More importantly, these digital-input Class D amplifiersprovide additional benefits of reduced power, complexity, noise, and system cost.

    標(biāo)簽: 數(shù)字輸入放大器 系統(tǒng)設(shè)計(jì)

    上傳時(shí)間: 2013-12-20

    上傳用戶:JIUSHICHEN

  • 音頻數(shù)模轉(zhuǎn)換器DAC抖動(dòng)的靈敏度分析

    Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.

    標(biāo)簽: DAC 音頻 數(shù)模轉(zhuǎn)換器 抖動(dòng)

    上傳時(shí)間: 2013-10-25

    上傳用戶:banyou

  • MAX5713-MAX5715數(shù)據(jù)資料

    The MAX5713/MAX5714/MAX5715 4-channel, low-power,8-/10-/12-bit, voltage-output digital-to-analog converters(DACs) include output buffers and an internal referencethat is selectable to be 2.048V, 2.500V, or 4.096V. TheMAX5713/MAX5714/MAX5715 accept a wide supplyvoltage range of 2.7V to 5.5V with extremely low power(3mW) consumption to accommodate most low-voltageapplications. A precision external reference input allowsrail-to-rail operation and presents a 100kI (typ) load toan external reference.

    標(biāo)簽: MAX 5713 5715 數(shù)據(jù)資料

    上傳時(shí)間: 2013-12-23

    上傳用戶:ArmKing88

  • 數(shù)控DCDC轉(zhuǎn)換器在便攜產(chǎn)品中的應(yīng)用

    Abstract: This tutorial discusses methods for digitally adjusting the output voltage of a DC-DC converter. The digital adjustmentmethods are with a digital-to-analog converter (DAC), a trim pot (digital potentiometer), and PWM output of a microprocessor.Each method is assessed and several DACs and digital potentiometers presented.

    標(biāo)簽: DCDC 數(shù)控 便攜產(chǎn)品 中的應(yīng)用

    上傳時(shí)間: 2013-11-20

    上傳用戶:zycidjl

  • 加載,感應(yīng)DAC應(yīng)用

    Abstract: This article discusses application circuits for Maxim force/sense digital-to-analog converters (DACs). Applications include:selectable fixed-gain DAC, programmable gain DAC, photodiode bias control, amperometric sensor control, digitally programmablecurrent source, Kelvin load sensing, temperature sensing, and high current DAC output. A brief description of the various DAC outputconfigurations is also given.

    標(biāo)簽: DAC

    上傳時(shí)間: 2013-11-04

    上傳用戶:youmo81

  • 數(shù)字集成電路設(shè)計(jì)Digital Integrated Circuit Design

      This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.

    標(biāo)簽: Integrated Digital Circuit Design

    上傳時(shí)間: 2013-11-04

    上傳用戶:life840315

  • 高集成四通道工業(yè)控制應(yīng)用的電壓輸出DAC

      Digital-to-analog converters (DACs) are prevalent inindustrial control and automated test applications.General-purpose automated test equipment often requiresmany channels of precisely controlled voltagesthat span several voltage ranges. The LTC2704 is ahighly integrated 16-bit, 4-channel DAC for high-endapplications. It has a wide range of features designed toincrease performance and simplify design.

    標(biāo)簽: DAC 集成 四通道 工業(yè)

    上傳時(shí)間: 2013-11-22

    上傳用戶:元宵漢堡包

  • 針對(duì)遠(yuǎn)程系統(tǒng)的小型溫度傳感器 (tiny temperatu

    The LM20, LM45, LM50, LM60, LM61, and LM62 are analog output temperature sensors. They have various output voltage slopes (6.25mV/°C to 17mV/°C) and power supply voltage ranges (2.4V to 10V).The LM20 is the smallest, lowest power consumption analog output temperature sensor National Semiconductor has released. The LM70 and LM74 are MICROWIRE/SPI compatible digital temperature sensors. The LM70 has a resolution of 0.125°C while the LM74 has a resolution of 0.625°C. The LM74 is the most accurate of the two with an accuracy better than ±1.25°C. The LM75 is National’s first digital output temperature sensor, released several years ago.

    標(biāo)簽: temperatu tiny 遠(yuǎn)程系統(tǒng) 溫度傳感器

    上傳時(shí)間: 2014-12-23

    上傳用戶:yl8908

  • DAC技術(shù)用語(yǔ) (D/A Converters Defini

    Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.

    標(biāo)簽: Converters Defini DAC

    上傳時(shí)間: 2013-10-30

    上傳用戶:stvnash

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