This methodical text aspires to present various information relevant to operating systems, computer Architecture, compilers, principles of programming languages, and C and C++ programming, specifically.
The release of the Microsoft Visual Studio .NET (and Visual C++ .NET in particular) has underscored Microsoft’s increasing focus on Internet technologies, which are at the heart of the Microsoft .NET Architecture. In addition to supporting the .NET initiative, Visual C++ .
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families
(hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard
Architecture that has one program memory bus and three data memory buses. These processors also provide
an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip
memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction
set, which is the basis of the operational flexibility and speed of these DSPs.
FatFs06.rar
FatFs is a generic file system module to implement the FAT file system to small embedded systems. The FatFs is written in compliance with ANSI C, therefore it is independent of hardware Architecture. It can be incorporated into cheap microcontrollers, such as 8051, PIC, AVR, SH, Z80, H8, ARM and etc..., without any change.
The System Management BIOS Reference Specification addresses how motherboard and system vendors present
management information about their products in a standard format by extending the BIOS interface on Intel
Architecture systems. The information is intended to allow generic instrumentation to deliver this data to
management applications that use CIM (the WBEM data model) or direct access and eliminates the need for error
prone operations like probing system hardware for presence detection.
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II Architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
Batch version of the back-propagation algorithm.
％ Given a set of corresponding input-output pairs and an initial network
％ [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the
％ network with backpropagation.
％
％ The activation functions must be either linear or tanh. The network
％ Architecture is defined by the matrix NetDef consisting of two
％ rows. The first row specifies the hidden layer while the second
％ specifies the output layer.
％
％ Train a two layer neural network with the Levenberg-Marquardt
％ method.
％
％ If desired, it is possible to use regularization by
％ weight decay. Also pruned (ie. not fully connected) networks can
％ be trained.
％
％ Given a set of corresponding input-output pairs and an initial
％ network,
％ [W1,W2,critvec,iteration,lambda]=marq(NetDef,W1,W2,PHI,Y,trparms)
％ trains the network with the Levenberg-Marquardt method.
％
％ The activation functions can be either linear or tanh. The
％ network Architecture is defined by the matrix NetDef which
％ has two rows. The first row specifies the hidden layer and the
％ second row specifies the output layer.
