This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標簽： FPGA 安全系統(tǒng)
上傳時間： 2013-11-05
上傳用戶：維子哥哥
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時間： 2013-10-22
上傳用戶：ztj182002
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
上傳時間： 2014-12-28
上傳用戶：康郎
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間： 2014-08-16
上傳用戶：adada
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現(xiàn)了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調(diào)的原理和實現(xiàn)方法，推導出一種簡便的引入?仔/4固定相移的實現(xiàn)方法。采用模塊化的設計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實現(xiàn)了整個系統(tǒng)。測試結果表明該系統(tǒng)正確實現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-06
上傳用戶：liu123
很多不同的廠家生產(chǎn)各種型號的計算機，它們運行完全不同的操作系統(tǒng)，但TCP.IP協(xié)議族允許它們互相進行通信。這一點很讓人感到吃驚，因為它的作用已遠遠超出了起初的設想。T C P / I P起源于6 0年代末美國政府資助的一個分組交換網(wǎng)絡研究項目，到9 0年代已發(fā)展成為計算機之間最常應用的組網(wǎng)形式。它是一個真正的開放系統(tǒng)，因為協(xié)議族的定義及其多種實現(xiàn)可以不用花錢或花很少的錢就可以公開地得到。它成為被稱作“全球互聯(lián)網(wǎng)”或“因特網(wǎng)(Internet)”的基礎，該廣域網(wǎng)（WA N）已包含超過1 0 0萬臺遍布世界各地的計算機。本章主要對T C P / I P協(xié)議族進行概述，其目的是為本書其余章節(jié)提供充分的背景知識。 TCP.IP協(xié)議 縮略語 ACK (ACKnowledgment) TCP首部中的確認標志 API (Application Programming Interface) 應用編程接口 ARP (Address Resolution Protocol) 地址解析協(xié)議 ARPANET(Defense Advanced Research Project Agency NETwork) (美國)國防部遠景研究規(guī)劃局 AS (Autonomous System) 自治系統(tǒng) ASCII (American Standard Code for Information Interchange) 美國信息交換標準碼 ASN.1 (Abstract Syntax Notation One) 抽象語法記法1 BER (Basic Encoding Rule) 基本編碼規(guī)則 BGP (Border Gateway Protocol) 邊界網(wǎng)關協(xié)議 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引導程序協(xié)議 BPF (BSD Packet Filter) BSD 分組過濾器 CIDR (Classless InterDomain Routing) 無類型域間選路 CIX (Commercial Internet Exchange) 商業(yè)互聯(lián)網(wǎng)交換 CLNP (ConnectionLess Network Protocol) 無連接網(wǎng)絡協(xié)議 CRC (Cyclic Redundancy Check) 循環(huán)冗余檢驗 CSLIP (Compressed SLIP) 壓縮的S L I P CSMA (Carrier Sense Multiple Access) 載波偵聽多路存取 DCE (Data Circuit-terminating Equipment) 數(shù)據(jù)電路端接設備 DDN (Defense Data Network) 國防數(shù)據(jù)網(wǎng) DF (Don’t Fragment) IP首部中的不分片標志 DHCP (Dynamic Host Configuration Protocol) 動態(tài)主機配置協(xié)議 DLPI (Data Link Provider Interface) 數(shù)據(jù)鏈路提供者接口 DNS (Domain Name System) 域名系統(tǒng) DSAP (Destination Service Access Point) 目的服務訪問點 DSLAM (DSL Access Multiplexer) 數(shù)字用戶線接入復用器 DSSS (Direct Sequence Spread Spectrum) 直接序列擴頻 DTS (Distributed Time Service) 分布式時間服務 DVMRP (Distance Vector Multicast Routing Protocol) 距離向量多播選路協(xié)議 EBONE (European IP BackbONE) 歐洲I P主干網(wǎng) EOL (End of Option List) 選項清單結束 EGP (External Gateway Protocol) 外部網(wǎng)關協(xié)議 EIA (Electronic Industries Association) 美國電子工業(yè)協(xié)會 FCS (Frame Check Sequence) 幀檢驗序列 FDDI (Fiber Distributed Data Interface) 光纖分布式數(shù)據(jù)接口 FIFO (First In, First Out) 先進先出 FIN (FINish) TCP首部中的結束標志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件傳送協(xié)議 HDLC (High-level Data Link Control) 高級數(shù)據(jù)鏈路控制 HELLO 選路協(xié)議 IAB (Internet Architecture Board) Internet體系結構委員會 IANA (Internet Assigned Numbers Authority) Internet號分配機構 ICMP (Internet Control Message Protocol) Internet控制報文協(xié)議 IDRP (InterDomain Routing Protocol) 域間選路協(xié)議 IEEE (Institute of Electrical and Electronics Engineering) （美國）電氣與電子工程師協(xié)會 IEN (Internet Experiment Notes) 互聯(lián)網(wǎng)試驗注釋 IESG (Internet Engineering Steering Group) Internet工程指導小組 IETF (Internet Engineering Task Force) Internet工程專門小組 IGMP (Internet Group Management Protocol) Internet組管理協(xié)議 IGP (Interior Gateway Protocol) 內(nèi)部網(wǎng)關協(xié)議 IMAP (Internet Message Access Protocol) Internet報文存取協(xié)議 IP (Internet Protocol) 網(wǎng)際協(xié)議 I RTF (Internet Research Task Force) Internet研究專門小組 IS-IS (Intermediate System to Intermediate System Protocol) 中間系統(tǒng)到中間系統(tǒng)協(xié)議 ISN (Initial Sequence Number) 初始序號 ISO (International Organization for Standardization) 國際標準化組織 ISOC (Internet SOCiety) Internet協(xié)會 LAN (Local Area Network) 局域網(wǎng) LBX (Low Bandwidth X) 低帶寬X LCP (Link Control Protocol) 鏈路控制協(xié)議 LFN (Long Fat Net) 長肥網(wǎng)絡 LIFO (Last In, First Out) 后進先出 LLC (Logical Link Control) 邏輯鏈路控制 LSRR (Loose Source and Record Route) 寬松的源站及記錄路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干網(wǎng) MIB (Management Information Base) 管理信息庫 MILNET (MILitary NETwork) 軍用網(wǎng) MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t郵件擴充 MSL (Maximum Segment Lifetime) 報文段最大生存時間 MSS (Maximum Segment Size) 最大報文段長度 M TA (Message Transfer Agent) 報文傳送代理 MTU (Maximum Transmission Unit) 最大傳輸單元 NCP (Network Control Protocol) 網(wǎng)絡控制協(xié)議 NFS (Network File System) 網(wǎng)絡文件系統(tǒng) NIC (Network Information Center) 網(wǎng)絡信息中心 NIT (Network Interface Tap) 網(wǎng)絡接口栓（S u n公司的一個程序） NNTP (Network News Transfer Protocol) 網(wǎng)絡新聞傳送協(xié)議 NOAO (National Optical Astronomy Observatories) 國家光學天文臺 NOP (No Operation) 無操作 NSFNET (National Science Foundation NETwork) 國家科學基金網(wǎng)絡 NSI (NASA Science Internet) （美國）國家宇航局I n t e r n e t NTP (Network Time Protocol) 網(wǎng)絡時間協(xié)議 NVT (Network Virtual Terminal) 網(wǎng)絡虛擬終端 OSF (Open Software Foudation) 開放軟件基金 OSI (Open Systems Interconnection) 開放系統(tǒng)互連 OSPF (Open Shortest Path First) 開放最短通路優(yōu)先 PAWS (Protection Against Wrapped Sequence number) 防止回繞的序號 PDU (Protocol Data Unit) 協(xié)議數(shù)據(jù)單元 POSIX (Portable Operating System Interface) 可移植操作系統(tǒng)接口 PPP (Point-to-Point Protocol) 點對點協(xié)議 PSH (PuSH) TCP首部中的急迫標志 RARP (Reverse Address Resolution Protocol) 逆地址解析協(xié)議 RFC (Request For Comments) Internet的文檔，其中的少部分成為標準文檔 RIP (Routing Information Protocol) 路由信息協(xié)議 RPC (Remote Procedure Call) 遠程過程調(diào)用 RR (Resource Record) 資源記錄 RST (ReSeT) TCP首部中的復位標志 RTO (Retransmission Time Out) 重傳超時 RTT (Round-Trip Time) 往返時間 SACK (Selective ACKnowledgment) 有選擇的確認 SLIP (Serial Line Internet Protocol) 串行線路I n t e r n e t協(xié)議 SMI (Structure of Management Information) 管理信息結構 SMTP (Simple Mail Transfer Protocol) 簡單郵件傳送協(xié)議 SNMP (Simple Network Management Protocol) 簡單網(wǎng)絡管理協(xié)議 SSAP (Source Service Access Point) 源服務訪問點 SSRR (Strict Source and Record Route) 嚴格的源站及記錄路由 SWS (Silly Window Syndrome) 糊涂窗口綜合癥 SYN (SYNchronous) TCP首部中的同步序號標志 TCP (Transmission Control Protocol) 傳輸控制協(xié)議 TFTP (Trivial File Transfer Protocol) 簡單文件傳送協(xié)議 TLI (Transport Layer Interface) 運輸層接口 TTL (Ti m e - To-Live) 生存時間或壽命 TUBA (TCP and UDP with Bigger Addresses) 具有更長地址的T C P和U D P Telnet 遠程終端協(xié)議 UA (User Agent) 用戶代理 UDP (User Datagram Protocol) 用戶數(shù)據(jù)報協(xié)議 URG (URGent) TCP首部中的緊急指針標志 UTC (Coordinated Universal Time) 協(xié)調(diào)的統(tǒng)一時間 UUCP (Unix-to-Unix CoPy) Unix到U n i x的復制 WAN (Wide Area Network) 廣域網(wǎng) WWW (World Wide Web) 萬維網(wǎng) XDR (eXternal Data Representation) 外部數(shù)據(jù)表示 XID (transaction ID) 事務標識符 XTI (X/Open Transport Layer Interface) X/ O p e n運輸層接口
上傳時間： 2013-11-13
上傳用戶：tdyoung
In today’s world of modular networking and telecommunications design, it is becomingincreasingly difficult to keep alignment with the many different and often changing interfaces,both inter-board and intra-board. Each manufacturer has their own spin on the way in whichdevices are connected. To satisfy the needs of our customers, we must be able to support alltheir interface requirements. For us to be able to make products for many customers, we mustadopt a modular approach to the design. This modularity is the one issue that drives the majorproblem of shifting our bits from one modular interface to another.
上傳時間： 2013-11-25
上傳用戶：suicone
主機板(簡稱Mother Board)是計算機主機的軀體，它承載用戶操作使用的各類設備，負責設備的數(shù)據(jù)處理和控制
標簽： 主機
上傳時間： 2014-12-29
上傳用戶：q986086481
A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
上傳時間： 2013-11-05
上傳用戶：Wwill
