中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時(shí)間： 2013-11-19
上傳用戶：yyyyyyyyyy
摘要: 串行傳輸技術(shù)具有更高的傳輸速率和更低的設(shè)計(jì)成本, 已成為業(yè)界首選, 被廣泛應(yīng)用于高速通信領(lǐng)域。提出了一種新的高速串行傳輸接口的設(shè)計(jì)方案, 改進(jìn)了Aurora 協(xié)議數(shù)據(jù)幀格式定義的弊端, 并采用高速串行收發(fā)器Rocket I/O, 實(shí)現(xiàn)數(shù)據(jù)率為2.5 Gbps的高速串行傳輸。關(guān)鍵詞: 高速串行傳輸; Rocket I/O; Aurora 協(xié)議 為促使FPGA 芯片與串行傳輸技術(shù)更好地結(jié)合以滿足市場(chǎng)需求, Xilinx 公司適時(shí)推出了內(nèi)嵌高速串行收發(fā)器RocketI/O 的Virtex II Pro 系列FPGA 和可升級(jí)的小型鏈路層協(xié)議———Aurora 協(xié)議。Rocket I/O支持從622 Mbps 至3.125 Gbps的全雙工傳輸速率, 還具有8 B/10 B 編解碼、時(shí)鐘生成及恢復(fù)等功能, 可以理想地適用于芯片之間或背板的高速串行數(shù)據(jù)傳輸。Aurora 協(xié)議是為專有上層協(xié)議或行業(yè)標(biāo)準(zhǔn)的上層協(xié)議提供透明接口的第一款串行互連協(xié)議, 可用于高速線性通路之間的點(diǎn)到點(diǎn)串行數(shù)據(jù)傳輸, 同時(shí)其可擴(kuò)展的帶寬, 為系統(tǒng)設(shè)計(jì)人員提供了所需要的靈活性[4]。但該協(xié)議幀格式的定義存在弊端,會(huì)導(dǎo)致系統(tǒng)資源的浪費(fèi)。本文提出的設(shè)計(jì)方案可以改進(jìn)Aurora 協(xié)議的固有缺陷,提高系統(tǒng)性能, 實(shí)現(xiàn)數(shù)據(jù)率為2.5 Gbps 的高速串行傳輸, 具有良好的可行性和廣闊的應(yīng)用前景。
標(biāo)簽： Rocket 2.5 高速串行 收發(fā)器
上傳時(shí)間： 2013-11-06
上傳用戶：smallfish
計(jì)算機(jī)第五版英文版
標(biāo)簽： 計(jì)算機(jī)網(wǎng)絡(luò)
上傳時(shí)間： 2013-11-16
上傳用戶：我們的船長(zhǎng)
接收機(jī)和收信機(jī)指標(biāo) 接收機(jī), 指標(biāo) 接收機(jī)和收信機(jī)的指標(biāo)差距有靈敏度
標(biāo)簽： 收信機(jī)
上傳時(shí)間： 2013-10-20
上傳用戶：aesuser
五款信號(hào)完整性仿真分析工具
標(biāo)簽： 信號(hào)完整性 仿真分析
上傳時(shí)間： 2013-10-28
上傳用戶：Jerry_Chow
G0606M-I光電二極管 中文數(shù)據(jù)手冊(cè)
上傳時(shí)間： 2013-10-15
上傳用戶：firstbyte
芯達(dá)STM32入門系列教程之五《如何安裝RealView_MDK軟件》
標(biāo)簽： RealView_MDK STM 32 教程
上傳時(shí)間： 2013-10-10
上傳用戶：黃蛋的蛋黃
STM32神舟I號(hào)從入門到精通2012年3月版
標(biāo)簽： 2012 STM 32 神舟I號(hào)
上傳時(shí)間： 2013-11-02
上傳用戶：ABC677339
本會(huì)議將討論某些安全特性，將i.MX系列中各處理器所支持的特性進(jìn)行逐一比較。此外，本會(huì)議還將介紹如何啟用這些安全特性，包括代碼簽名和保險(xiǎn)絲熔斷工具。
標(biāo)簽： MX 應(yīng)用處理器 架構(gòu)
上傳時(shí)間： 2013-10-20
上傳用戶：zengduo
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