Chapter 1. Creational Patterns Chapter 2. Behavioral Patterns Chapter 3. Structural Patterns Chapter 4. System Patterns Chapter 5. Introduction to Java Programming Language Patterns Chapter 6. Java Core APIs Chapter 7. Distributed Technologies Chapter 8. Jini and J2EE Architectures
標簽： Patterns Chapter Behavioral Creational
上傳時間： 2014-02-02
上傳用戶：bakdesec
PacoBlaze is a from-scratch synthesizable & Behavioral Verilog clone of Ken Chapman s popular PicoBlaze embedded microcontroller. by Pablo Bleyer Kocik
標簽： synthesizable from-scratch Behavioral PacoBlaze
上傳時間： 2013-12-09
上傳用戶：hphh
A software solution for the control of visual Behavioral experimentation
標簽： experimentation Behavioral software solution
上傳時間： 2013-12-21
上傳用戶：獨孤求源
一篇優秀的博士論文,題目是 A particle swarm optimization based Behavioral and probabilistic fire evacuation model incorporating fire hazards and human behaviors
標簽： probabilistic optimization Behavioral evacuation
上傳時間： 2013-12-22
上傳用戶：waitingfy
arm10-Behavioral的行為仿真代碼ｖｅｒｉｌｏｇＨＤＬ
標簽： Behavioral arm 10 仿真
上傳時間： 2014-11-05
上傳用戶：zhenyushaw
Booths Multiplier using Behavioral Model
標簽： Behavioral Multiplier Booths Model
上傳時間： 2017-05-21
上傳用戶：lmeeworm
Up-down Asynchronous counter in Behavioral Model
標簽： Asynchronous Behavioral Up-down counter
上傳時間： 2017-05-21
上傳用戶：caozhizhi
Behavioral models are used in games and computer graphics for realistic simulation of massive crowds. In this paper, we present a GPU based implementation of Reynolds [1987] algorithm for simulating flocks of birds and propose an extension to consider environment self occlusion. We performed several experiments and the results showed that the proposed approach runs up to three times faster than the original algorithm when simulating high density crowds, without compromising significantly the original crowd behavior.
標簽： Behavioral simulation realistic computer
上傳時間： 2017-09-08
上傳用戶：hanli8870
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing Behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
怎樣寫testbench-xilinx 在ISE 環境中， 當前資源操作窗顯示了資源管理窗口中選中的資源文件能進行的相關操作。在資源管理窗口選中了 testbench 文件后，在當前資源操作窗顯示的 ModelSim Simulator 中顯示了4種能進行的模擬操作，分別是：Simulator Behavioral Model（功能仿真）、Simulator Post-translate VHDL Model（翻譯后仿真）、Simulator Post-Map VHDL Model（映射后仿真）、Simulator Post-Place & Route VHDL Model（布局布線后仿真） 。如
標簽： testbench-xilinx
上傳時間： 2013-11-14
上傳用戶：467368609
