demonstrates how to use
Delphi with WinLIRC. The source-code is included and there is also a
binary file. It runs with Delphi versions 3 through 7. No special components
are required.
Short description: A MAX-MIN Ant System (MMAS) implemented in the Hyper-Cube Framework for the application to Unconstrained Binary Quadratic Programming (UBQP).
Aim of the software: Educational (not high-performance) it shows how to implement a MMAS in the Hyper-Cube Framework.
This program is to find the floating point representation of real number.
The user will be asked for the number of mantissa, exponential, and the real number to be calculated (R=10).
The program will find the FPR for Hexadecimal (R=16), Octal (R=8), and Binary (R=2).
Web based binary image upload for ARM LPC2366 controller. Toolchain is Keil Realview MDK ARM ver 3.2 with RL ARM Real time Lib 3.40. RAR file contains webiap2.cgi file and HTTP_cgi file. HTTP_cgi file is modified in cgi_process_data to upload binary image of application using HTTP protcol. File upload is using HTML syntax method=\"post\" ENCTYPE=\"multipart/form-data\
a simple serial to parallel converter using XILLINX and VHDL (the number of the project represents the binary code used by the converter e.g 23- 10111)
The FPGA can realize a more optimized Digital controller in DC/DC Converters when compare to DSPs. In this paper, based on the FPGA platform, The theoretical analysis, characteristics, simulation and design consideration are given. The methods to implement the digital DC/DC Converters have been researched. The function module, state machine of digital DC/DC controller and high resolution DPWM with Sigma-
Delta dither has been introduced. They are verified by experiments on a 20 W, 300 KHz non-isolated synchronous buck converters.
In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx
Alliance tools and Synplicity Synplify.
RS_latch using vhdl,
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q.
Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
MBUS協(xié)議
The bus communication system of EN1434-3 is commonly called M-Bus. Its application layer describes
a standard especially for meter readout. It can be used with various physical layers and with link layers
and network layers which support the transmission of variable length binary transparent telegrams.
The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. This contribution attempts to provide a state-of-the-art description of this topic. First, the advantages of reconfigurable hardware for cryptographic applications are discussed from a systems perspective. Second, potential security problems of FPGAs are described in detail, followed by a proposal of a some countermeasure. Third, a list of open research problems is provided. Even though there have been many contributions dealing with the algorithmic
aspects of cryptographic schemes implemented on FPGAs, this contribution appears to be the first comprehensive treatment of system and security aspects.
