18B20和單總線的時序及其工作原理,51單片機控制的18B20程序(包括多個18B20的程序)18B20 and single-bus timing and its working principle, control of 51 single-CHip 18B20 procedures (including procedures for more than 18B20)
標簽： 18B20 single-bus and principl
上傳時間： 2017-08-10
上傳用戶：wang5829
A programmable digital signal processor (PDSP) is a special-purpose microprocessor with specialized architecture and instruction set for implementing DSP algorithms. Typical architectural features include multiple memory partitions (onCHip, off-CHip, data memory, program memory, etc.), multiple (generally pipelined) arithmetic and logic units (ALUs), nonuniform register sets, and extensive hardware numeric support [1,2]. Single-CHip PDSPs have become increasingly popular for real-time DSP applications [3,4].
標簽： special-purpose microprocessor programmable specialized
上傳時間： 2017-08-13
上傳用戶：腳趾頭
The potential of solving real-time demanding industrial applications, using vision-based algorithms, drastically grew due to an increasing availability of computational power. In this thesis a novel real-time, vision-based Blackjack analysis system is presented. The embedding of the vision algorithms in a compound system of other information sources such as an electronic CHip tray, reduces the vision task to detect cards and CHips. Robust results are achieved by not just analyzing single frames but an image stream regarding game-ß ow informations. The requirements for such a system are a highly robust and adaptive behav- ior. This is motivated by the vital interest of casino entrepreneurs in a 100 statistical analysis of their offered gambling in order to support the business plan, measuring table and dealer performance and give accurate player rating. Extensive experiments show the robustness and applicability of the proposed system.
標簽： applications vision-based algorithms industrial
上傳時間： 2017-08-20
上傳用戶：liansi
This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2410X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (CHip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽： This microprocessor describes S3C2410X
上傳時間： 2014-01-11
上傳用戶：shizhanincc
The STi7105 uses state of the art process technology to provide an ultra low-cost, fully featured HD AVC decoder IC. It is a highly integrated system-on-CHip suitable for STB markets across all networks (cable/satellite/DTT/x- DSL/IP) worldwide
標簽： technology low-cost featured process
上傳時間： 2013-12-22
上傳用戶：時代電子小智
Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-CHip solutions using commodity FPGAs.
標簽： composition components hardware creation
上傳時間： 2017-09-24
上傳用戶：huql11633
An Overview of Smart Card Security. The smart card, an intelligent token, is a credit card sized plastic card embedded with an integrated circuit CHip. It provides not only memory capacity, but computational capability as well. The self-containment of smart card makes it resistant to attack as it does not need to depend upon potentially vulnerable external resources. Because of this characteristic, smart cards are often used in different applications which require strong security protection and authentication.
標簽： card intelligent Overview Security
上傳時間： 2017-09-25
上傳用戶：busterman
鉭電容封裝，從A-E都有，方便用于使用鉭電容設計的電路，希望對大家能有幫助
上傳時間： 2015-03-01
上傳用戶：久久jiujiu
FILE NAME: dc_motor.c CHip TYPE: ATMEGA16 CLOCK FREQUENCY: 8MHZ IDE: VSMStudio COMPILER: AVR-GCC
標簽： PWM
上傳時間： 2015-03-01
上傳用戶：abilibili
隨著微電子技術的迅猛發展，集成電路組成的電子系統集成度越來越高，使得芯片 的復雜性不斷上升，單片的成本卻不斷降低。FPGA產品的邏輯單元越來越多，性能越 來越高，單位成本和功耗向越來越低的方向發展，使得可編程片上系統SOPC(System On Programmable CHip)設計成為必然趨勢。SD存儲卡因具備體積小、儲容量高、可擦寫、 價格低以及非易失性等特點被廣泛應用于手機、數碼相機、MP3播放器等領域。 美國Altera公司開發的基于SOPC技術的Nios U嵌入式處理器，是一個可變結構、 通用型的32位RISC嵌入式處理器，設計者可以非常方便地使用SOPC Builder系統開 發工具設計構造以處理器為基礎的系統，針對自己的要求配置Nios II軟核、Avalon總 線及外圍接口系統，體現了面向用戶，面向應用的SOPC技術設計思想。應用與Nios II 相關的集成開發平臺和輔助開發工具，加快了NiosⅡ系統的設計與驗證環節的開發速 度，對于嵌入式系統的產品開發和應用，具有廣泛的價值和積極的意義。 本文介紹了基于Nios II嵌入式處理器的SOPC系統的軟、硬件設計方法，結合實 驗平臺資源特點，構建了基于Nios II軟核處理器的SD
上傳時間： 2015-05-25
上傳用戶：wjc511
