This is GPS in matlab calculatePseudoranges finds relative pseudoranges for all satellites listed in CHANNELLIST at the specified millisecond of the processed signal. The pseudoranges contain unknown receiver clock offset. It can be found by the least squares position search procedure.
標簽： calculatePseudoranges pseudoranges satellites relative
上傳時間： 2017-03-09
上傳用戶：時代電子小智
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
標簽： Peripheral Interface available Enhanced
上傳時間： 2014-12-06
上傳用戶：invtnewer
Decimal counter which is counting from 256 to 0. After that there will appear logic "1" in out. You can stop counting by pressing sequence. I called it detonation clock :]
標簽： counting Decimal counter appear
上傳時間： 2014-10-13
上傳用戶：731140412
TLC548和TLC549是以8位開關電容逐次逼近A/D轉換器為基礎而構造的CMOS A/D轉換器。它們設 計成能通過3態數據輸出和模擬輸入與微處理器或外圍設備串行接口。TLC548和TLC549僅用輸入/輸出時 鐘（I/O CLOCK） 和芯片選擇（CS） 輸入作數據控制。TLC548的最高I/O CLOCK輸入頻率為2.048MHz， 而TLC549的I/O CLOCK輸入頻率最高可達1.1MHz。 有關與大多數通用微處理器接口的詳細資料已由工廠 準備好，可供使用。
上傳時間： 2013-11-28
上傳用戶：aig85
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assuming a 30Mhz XCLKIN). The clock divider in the ADC is not used so that the ADC will see the 25Mhz on the HSPCLK. Interrupts are enabled and the EVA is setup to generate a periodic ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
標簽： SYSCLKOUT example divides HSPCLK
上傳時間： 2014-01-25
上傳用戶：ljt101007
這是MFC Windows程序設計（第2版），書上的代碼。第14章，計時器，CLOCK應用程序，空閑處理的編程，供大家參考。
上傳時間： 2013-12-24
上傳用戶：wangyi39
三星程式范例，八位元的 timer, counter, serial I/O, clock switching, power down, key scan, A to D, software generated LCD control, ...
上傳時間： 2013-12-17
上傳用戶：zhengzg
Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
標簽： design hardware includes Encoder
上傳時間： 2013-12-15
上傳用戶：王者A
本模擬I2C軟件包包含了I2C操作的底層子程序，使用前要定義好SCL和SDA。在標準8051模式(12 Clock)下,對主頻要求是不高于12MHz
上傳時間： 2013-12-27
上傳用戶：330402686
This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽： This microprocessor describes S3C2410A
上傳時間： 2013-11-30
上傳用戶：GavinNeko
